Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* Copyright (C) 2003-2006, Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #ifndef _GEODE_AES_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #define _GEODE_AES_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) /* driver logic flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define AES_MODE_ECB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define AES_MODE_CBC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define AES_DIR_DECRYPT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AES_DIR_ENCRYPT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AES_FLAGS_HIDDENKEY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AES_CTRLA_REG  0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AES_CTRL_START     0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AES_CTRL_DECRYPT   0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AES_CTRL_ENCRYPT   0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AES_CTRL_WRKEY     0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AES_CTRL_DCA       0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AES_CTRL_SCA       0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AES_CTRL_CBC       0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AES_INTR_REG  0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AES_INTRA_PENDING (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AES_INTRB_PENDING (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AES_INTR_PENDING  (AES_INTRA_PENDING | AES_INTRB_PENDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AES_INTR_MASK     0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AES_SOURCEA_REG   0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AES_DSTA_REG      0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AES_LENA_REG      0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AES_WRITEKEY0_REG 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AES_WRITEIV0_REG  0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*  A very large counter that is used to gracefully bail out of an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  *  operation in case of trouble
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AES_OP_TIMEOUT    0x50000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct geode_aes_tfm_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	u8 key[AES_KEYSIZE_128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		struct crypto_skcipher *skcipher;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		struct crypto_cipher *cip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	} fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	u32 keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif