Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include "cc_driver.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include "cc_buffer_mgr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "cc_request_mgr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "cc_sram_mgr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "cc_hash.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "cc_pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "cc_fips.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define POWER_DOWN_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define POWER_DOWN_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static int cc_pm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	struct cc_drvdata *drvdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	dev_dbg(dev, "set HOST_POWER_DOWN_EN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	fini_cc_regs(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	clk_disable_unprepare(drvdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int cc_pm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	struct cc_drvdata *drvdata = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	dev_dbg(dev, "unset HOST_POWER_DOWN_EN\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	/* Enables the device source clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	rc = clk_prepare_enable(drvdata->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		dev_err(dev, "failed getting clock back on. We're toast.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	/* wait for Cryptocell reset completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	if (!cc_wait_for_reset_completion(drvdata)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		dev_err(dev, "Cryptocell reset not completed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	rc = init_cc_regs(drvdata, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		dev_err(dev, "init_cc_regs (%x)\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	/* check if tee fips error occurred during power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	cc_tee_handle_fips_error(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	cc_init_hash_sram(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) const struct dev_pm_ops ccree_pm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	SET_RUNTIME_PM_OPS(cc_pm_suspend, cc_pm_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int cc_pm_get(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	int rc = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void cc_pm_put_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	pm_runtime_mark_last_busy(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	pm_runtime_put_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }