^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /* \file cc_hash.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * ARM CryptoCell Hash Crypto API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __CC_HASH_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __CC_HASH_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "cc_buffer_mgr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define HMAC_IPAD_CONST 0x36363636
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define HMAC_OPAD_CONST 0x5C5C5C5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define HASH_LEN_SIZE_712 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HASH_LEN_SIZE_630 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HASH_MAX_LEN_SIZE HASH_LEN_SIZE_712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CC_MAX_HASH_DIGEST_SIZE SHA512_DIGEST_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CC_MAX_HASH_BLCK_SIZE SHA512_BLOCK_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define XCBC_MAC_K1_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define XCBC_MAC_K2_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define XCBC_MAC_K3_OFFSET 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CC_EXPORT_MAGIC 0xC2EE1070U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* this struct was taken from drivers/crypto/nx/nx-aes-xcbc.c and it is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * for xcbc/cmac statesize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct aeshash_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 state[AES_BLOCK_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 buffer[AES_BLOCK_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* ahash state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct ahash_req_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 buffers[2][CC_MAX_HASH_BLCK_SIZE] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 digest_result_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 opad_digest_buff[CC_MAX_HASH_DIGEST_SIZE] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 digest_bytes_len[HASH_MAX_LEN_SIZE] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct async_gen_req_ctx gen_ctx ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) enum cc_req_dma_buf_type data_dma_buf_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) dma_addr_t opad_digest_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) dma_addr_t digest_buff_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) dma_addr_t digest_bytes_len_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) dma_addr_t digest_result_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 buf_cnt[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 buff_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 xcbc_count; /* count xcbc update operatations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct scatterlist buff_sg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct scatterlist *curr_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 in_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 mlli_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct mlli_params mlli_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static inline u32 *cc_hash_buf_cnt(struct ahash_req_ctx *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return &state->buf_cnt[state->buff_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline u8 *cc_hash_buf(struct ahash_req_ctx *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return state->buffers[state->buff_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline u32 *cc_next_buf_cnt(struct ahash_req_ctx *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return &state->buf_cnt[state->buff_index ^ 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static inline u8 *cc_next_buf(struct ahash_req_ctx *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return state->buffers[state->buff_index ^ 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int cc_hash_alloc(struct cc_drvdata *drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int cc_init_hash_sram(struct cc_drvdata *drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int cc_hash_free(struct cc_drvdata *drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * cc_digest_len_addr() - Gets the initial digest length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @drvdata: Associated device driver context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @mode: The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Returns the address of the initial digest length in SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 cc_digest_len_addr(void *drvdata, u32 mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * cc_larval_digest_addr() - Gets the address of the initial digest in SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * according to the given hash mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @drvdata: Associated device driver context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @mode: The Hash mode. Supported modes: MD5/SHA1/SHA224/SHA256/SHA384/SHA512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * The address of the initial digest in SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 cc_larval_digest_addr(void *drvdata, u32 mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif /*__CC_HASH_H__*/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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