^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <crypto/algapi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <crypto/internal/skcipher.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <crypto/internal/des.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <crypto/xts.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <crypto/sm4.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <crypto/scatterwalk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "cc_driver.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "cc_lli_defs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "cc_buffer_mgr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "cc_cipher.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "cc_request_mgr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MAX_SKCIPHER_SEQ_LEN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define template_skcipher template_u.skcipher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct cc_user_key_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u8 *key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) dma_addr_t key_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct cc_hw_key_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum cc_hw_crypto_key key1_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum cc_hw_crypto_key key2_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct cc_cpp_key_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) enum cc_cpp_alg alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) enum cc_key_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) CC_UNPROTECTED_KEY, /* User key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) CC_HW_PROTECTED_KEY, /* HW (FDE) key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) CC_POLICY_PROTECTED_KEY, /* CPP key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) CC_INVALID_PROTECTED_KEY /* Invalid key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct cc_cipher_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct cc_drvdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int cipher_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int flow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum cc_key_type key_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct cc_user_key_info user;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct cc_hw_key_info hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct cc_cpp_key_info cpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct crypto_shash *shash_tfm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct crypto_skcipher *fallback_tfm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) bool fallback_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void cc_cipher_complete(struct device *dev, void *cc_req, int err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline enum cc_key_type cc_key_type(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return ctx_p->key_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int validate_keys_sizes(struct cc_cipher_ctx *ctx_p, u32 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) switch (ctx_p->flow_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case S_DIN_to_AES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case CC_AES_128_BIT_KEY_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) case CC_AES_192_BIT_KEY_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (ctx_p->cipher_mode != DRV_CIPHER_XTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) case CC_AES_256_BIT_KEY_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case (CC_AES_192_BIT_KEY_SIZE * 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case (CC_AES_256_BIT_KEY_SIZE * 2):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (ctx_p->cipher_mode == DRV_CIPHER_XTS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ctx_p->cipher_mode == DRV_CIPHER_ESSIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case S_DIN_to_DES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (size == DES3_EDE_KEY_SIZE || size == DES_KEY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case S_DIN_to_SM4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (size == SM4_KEY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int validate_data_size(struct cc_cipher_ctx *ctx_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) switch (ctx_p->flow_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) case S_DIN_to_AES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) switch (ctx_p->cipher_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case DRV_CIPHER_XTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) case DRV_CIPHER_CBC_CTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (size >= AES_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case DRV_CIPHER_OFB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case DRV_CIPHER_CTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case DRV_CIPHER_ECB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case DRV_CIPHER_CBC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case DRV_CIPHER_ESSIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (IS_ALIGNED(size, AES_BLOCK_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case S_DIN_to_DES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (IS_ALIGNED(size, DES_BLOCK_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case S_DIN_to_SM4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) switch (ctx_p->cipher_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case DRV_CIPHER_CTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case DRV_CIPHER_ECB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case DRV_CIPHER_CBC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (IS_ALIGNED(size, SM4_BLOCK_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int cc_cipher_init(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct cc_crypto_alg *cc_alg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) container_of(tfm->__crt_alg, struct cc_crypto_alg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) skcipher_alg.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct device *dev = drvdata_to_dev(cc_alg->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int max_key_buf_size = cc_alg->skcipher_alg.max_keysize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int fallback_req_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_dbg(dev, "Initializing context @%p for %s\n", ctx_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) crypto_tfm_alg_name(tfm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ctx_p->cipher_mode = cc_alg->cipher_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ctx_p->flow_mode = cc_alg->flow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ctx_p->drvdata = cc_alg->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const char *name = crypto_tfm_alg_name(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Alloc hash tfm for essiv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ctx_p->shash_tfm = crypto_alloc_shash("sha256", 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (IS_ERR(ctx_p->shash_tfm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev_err(dev, "Error allocating hash tfm for ESSIV.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return PTR_ERR(ctx_p->shash_tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) max_key_buf_size <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Alloc fallabck tfm or essiv when key size != 256 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ctx_p->fallback_tfm =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK | CRYPTO_ALG_ASYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (IS_ERR(ctx_p->fallback_tfm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Note we're still allowing registration with no fallback since it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * better to have most modes supported than none at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev_warn(dev, "Error allocating fallback algo %s. Some modes may be available.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ctx_p->fallback_tfm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) fallback_req_size = crypto_skcipher_reqsize(ctx_p->fallback_tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) crypto_skcipher_set_reqsize(__crypto_skcipher_cast(tfm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) sizeof(struct cipher_req_ctx) + fallback_req_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Allocate key buffer, cache line aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ctx_p->user.key = kzalloc(max_key_buf_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!ctx_p->user.key)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) goto free_fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) dev_dbg(dev, "Allocated key buffer in context. key=@%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ctx_p->user.key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Map key buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ctx_p->user.key_dma_addr = dma_map_single(dev, ctx_p->user.key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) max_key_buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (dma_mapping_error(dev, ctx_p->user.key_dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev_err(dev, "Mapping Key %u B at va=%pK for DMA failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) max_key_buf_size, ctx_p->user.key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) goto free_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dev_dbg(dev, "Mapped key %u B at va=%pK to dma=%pad\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) max_key_buf_size, ctx_p->user.key, &ctx_p->user.key_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) free_key:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) kfree(ctx_p->user.key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) free_fallback:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) crypto_free_skcipher(ctx_p->fallback_tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) crypto_free_shash(ctx_p->shash_tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void cc_cipher_exit(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct crypto_alg *alg = tfm->__crt_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct cc_crypto_alg *cc_alg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) container_of(alg, struct cc_crypto_alg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) skcipher_alg.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned int max_key_buf_size = cc_alg->skcipher_alg.max_keysize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct device *dev = drvdata_to_dev(ctx_p->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_dbg(dev, "Clearing context @%p for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) crypto_tfm_ctx(tfm), crypto_tfm_alg_name(tfm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Free hash tfm for essiv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) crypto_free_shash(ctx_p->shash_tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ctx_p->shash_tfm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) crypto_free_skcipher(ctx_p->fallback_tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ctx_p->fallback_tfm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Unmap key buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dma_unmap_single(dev, ctx_p->user.key_dma_addr, max_key_buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dev_dbg(dev, "Unmapped key buffer key_dma_addr=%pad\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) &ctx_p->user.key_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Free key buffer in context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_dbg(dev, "Free key buffer in context. key=@%p\n", ctx_p->user.key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) kfree_sensitive(ctx_p->user.key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct tdes_keys {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u8 key1[DES_KEY_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u8 key2[DES_KEY_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u8 key3[DES_KEY_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static enum cc_hw_crypto_key cc_slot_to_hw_key(u8 slot_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) switch (slot_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return KFDE0_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return KFDE1_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return KFDE2_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return KFDE3_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return END_OF_KEYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static u8 cc_slot_to_cpp_key(u8 slot_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return (slot_num - CC_FIRST_CPP_KEY_SLOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static inline enum cc_key_type cc_slot_to_key_type(u8 slot_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (slot_num >= CC_FIRST_HW_KEY_SLOT && slot_num <= CC_LAST_HW_KEY_SLOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return CC_HW_PROTECTED_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) else if (slot_num >= CC_FIRST_CPP_KEY_SLOT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) slot_num <= CC_LAST_CPP_KEY_SLOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return CC_POLICY_PROTECTED_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return CC_INVALID_PROTECTED_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int cc_cipher_sethkey(struct crypto_skcipher *sktfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct crypto_tfm *tfm = crypto_skcipher_tfm(sktfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct device *dev = drvdata_to_dev(ctx_p->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct cc_hkey_info hki;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_dbg(dev, "Setting HW key in context @%p for %s. keylen=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ctx_p, crypto_tfm_alg_name(tfm), keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dump_byte_array("key", key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* STAT_PHASE_0: Init and sanity checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* This check the size of the protected key token */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (keylen != sizeof(hki)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_err(dev, "Unsupported protected key size %d.\n", keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) memcpy(&hki, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* The real key len for crypto op is the size of the HW key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * referenced by the HW key slot, not the hardware key token
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) keylen = hki.keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (validate_keys_sizes(ctx_p, keylen)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dev_dbg(dev, "Unsupported key size %d.\n", keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ctx_p->keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ctx_p->fallback_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) switch (cc_slot_to_key_type(hki.hw_key1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case CC_HW_PROTECTED_KEY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ctx_p->flow_mode == S_DIN_to_SM4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev_err(dev, "Only AES HW protected keys are supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ctx_p->hw.key1_slot = cc_slot_to_hw_key(hki.hw_key1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (ctx_p->hw.key1_slot == END_OF_KEYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_err(dev, "Unsupported hw key1 number (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) hki.hw_key1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ctx_p->cipher_mode == DRV_CIPHER_XTS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ctx_p->cipher_mode == DRV_CIPHER_ESSIV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (hki.hw_key1 == hki.hw_key2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_err(dev, "Illegal hw key numbers (%d,%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) hki.hw_key1, hki.hw_key2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ctx_p->hw.key2_slot = cc_slot_to_hw_key(hki.hw_key2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (ctx_p->hw.key2_slot == END_OF_KEYS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev_err(dev, "Unsupported hw key2 number (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) hki.hw_key2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ctx_p->key_type = CC_HW_PROTECTED_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_dbg(dev, "HW protected key %d/%d set\n.",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ctx_p->hw.key1_slot, ctx_p->hw.key2_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) case CC_POLICY_PROTECTED_KEY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (ctx_p->drvdata->hw_rev < CC_HW_REV_713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev_err(dev, "CPP keys not supported in this hardware revision.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (ctx_p->cipher_mode != DRV_CIPHER_CBC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ctx_p->cipher_mode != DRV_CIPHER_CTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_err(dev, "CPP keys only supported in CBC or CTR modes.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ctx_p->cpp.slot = cc_slot_to_cpp_key(hki.hw_key1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ctx_p->flow_mode == S_DIN_to_AES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ctx_p->cpp.alg = CC_CPP_AES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) else /* Must be SM4 since due to sethkey registration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ctx_p->cpp.alg = CC_CPP_SM4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ctx_p->key_type = CC_POLICY_PROTECTED_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev_dbg(dev, "policy protected key alg: %d slot: %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ctx_p->cpp.alg, ctx_p->cpp.slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_err(dev, "Unsupported protected key (%d)\n", hki.hw_key1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int cc_cipher_setkey(struct crypto_skcipher *sktfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct crypto_tfm *tfm = crypto_skcipher_tfm(sktfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct device *dev = drvdata_to_dev(ctx_p->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct cc_crypto_alg *cc_alg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) container_of(tfm->__crt_alg, struct cc_crypto_alg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) skcipher_alg.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned int max_key_buf_size = cc_alg->skcipher_alg.max_keysize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_dbg(dev, "Setting key in context @%p for %s. keylen=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ctx_p, crypto_tfm_alg_name(tfm), keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dump_byte_array("key", key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* STAT_PHASE_0: Init and sanity checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (validate_keys_sizes(ctx_p, keylen)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_dbg(dev, "Invalid key size %d.\n", keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* We only support 256 bit ESSIV-CBC-AES keys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (keylen != AES_KEYSIZE_256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned int flags = crypto_tfm_get_flags(tfm) & CRYPTO_TFM_REQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (likely(ctx_p->fallback_tfm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ctx_p->fallback_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) crypto_skcipher_clear_flags(ctx_p->fallback_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) CRYPTO_TFM_REQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) crypto_skcipher_clear_flags(ctx_p->fallback_tfm, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return crypto_skcipher_setkey(ctx_p->fallback_tfm, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dev_dbg(dev, "Unsupported key size %d and no fallback.\n", keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Internal ESSIV key buffer is double sized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) max_key_buf_size <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ctx_p->fallback_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ctx_p->key_type = CC_UNPROTECTED_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * Verify DES weak keys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * Note that we're dropping the expanded key since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * HW does the expansion on its own.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (ctx_p->flow_mode == S_DIN_to_DES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if ((keylen == DES3_EDE_KEY_SIZE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) verify_skcipher_des3_key(sktfm, key)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) verify_skcipher_des_key(sktfm, key)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_dbg(dev, "weak DES key");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (ctx_p->cipher_mode == DRV_CIPHER_XTS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) xts_check_key(tfm, key, keylen)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_dbg(dev, "weak XTS key");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* STAT_PHASE_1: Copy key to ctx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dma_sync_single_for_cpu(dev, ctx_p->user.key_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) max_key_buf_size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) memcpy(ctx_p->user.key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ctx_p->cipher_mode == DRV_CIPHER_ESSIV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* sha256 for key2 - use sw implementation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) err = crypto_shash_tfm_digest(ctx_p->shash_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ctx_p->user.key, keylen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ctx_p->user.key + keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev_err(dev, "Failed to hash ESSIV key.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) keylen <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dma_sync_single_for_device(dev, ctx_p->user.key_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) max_key_buf_size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ctx_p->keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dev_dbg(dev, "return safely");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int cc_out_setup_mode(struct cc_cipher_ctx *ctx_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) switch (ctx_p->flow_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) case S_DIN_to_AES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return S_AES_to_DOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case S_DIN_to_DES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return S_DES_to_DOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) case S_DIN_to_SM4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return S_SM4_to_DOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return ctx_p->flow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static void cc_setup_readiv_desc(struct crypto_tfm *tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct cipher_req_ctx *req_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned int ivsize, struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct device *dev = drvdata_to_dev(ctx_p->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int cipher_mode = ctx_p->cipher_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int flow_mode = cc_out_setup_mode(ctx_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int direction = req_ctx->gen_ctx.op_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dma_addr_t iv_dma_addr = req_ctx->gen_ctx.iv_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (ctx_p->key_type == CC_POLICY_PROTECTED_KEY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) switch (cipher_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case DRV_CIPHER_ECB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case DRV_CIPHER_CBC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case DRV_CIPHER_CBC_CTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case DRV_CIPHER_CTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) case DRV_CIPHER_OFB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* Read next IV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) hw_desc_init(&desc[*seq_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) set_dout_dlli(&desc[*seq_size], iv_dma_addr, ivsize, NS_BIT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) set_cipher_config0(&desc[*seq_size], direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) set_flow_mode(&desc[*seq_size], flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) set_cipher_mode(&desc[*seq_size], cipher_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (cipher_mode == DRV_CIPHER_CTR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) cipher_mode == DRV_CIPHER_OFB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) set_setup_mode(&desc[*seq_size], SETUP_WRITE_STATE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) set_setup_mode(&desc[*seq_size], SETUP_WRITE_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) (*seq_size)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) case DRV_CIPHER_XTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case DRV_CIPHER_ESSIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* IV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) hw_desc_init(&desc[*seq_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) set_setup_mode(&desc[*seq_size], SETUP_WRITE_STATE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) set_cipher_mode(&desc[*seq_size], cipher_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) set_cipher_config0(&desc[*seq_size], direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) set_flow_mode(&desc[*seq_size], flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) set_dout_dlli(&desc[*seq_size], iv_dma_addr, CC_AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) NS_BIT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) (*seq_size)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_err(dev, "Unsupported cipher mode (%d)\n", cipher_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static void cc_setup_state_desc(struct crypto_tfm *tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct cipher_req_ctx *req_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) unsigned int ivsize, unsigned int nbytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct device *dev = drvdata_to_dev(ctx_p->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int cipher_mode = ctx_p->cipher_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int flow_mode = ctx_p->flow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int direction = req_ctx->gen_ctx.op_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dma_addr_t iv_dma_addr = req_ctx->gen_ctx.iv_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) switch (cipher_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) case DRV_CIPHER_ECB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case DRV_CIPHER_CBC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case DRV_CIPHER_CBC_CTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case DRV_CIPHER_CTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case DRV_CIPHER_OFB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Load IV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) hw_desc_init(&desc[*seq_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr, ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) set_cipher_config0(&desc[*seq_size], direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) set_flow_mode(&desc[*seq_size], flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) set_cipher_mode(&desc[*seq_size], cipher_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (cipher_mode == DRV_CIPHER_CTR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) cipher_mode == DRV_CIPHER_OFB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) (*seq_size)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case DRV_CIPHER_XTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case DRV_CIPHER_ESSIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dev_err(dev, "Unsupported cipher mode (%d)\n", cipher_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void cc_setup_xex_state_desc(struct crypto_tfm *tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct cipher_req_ctx *req_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) unsigned int ivsize, unsigned int nbytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct device *dev = drvdata_to_dev(ctx_p->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int cipher_mode = ctx_p->cipher_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int flow_mode = ctx_p->flow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int direction = req_ctx->gen_ctx.op_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dma_addr_t key_dma_addr = ctx_p->user.key_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) unsigned int key_len = (ctx_p->keylen / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dma_addr_t iv_dma_addr = req_ctx->gen_ctx.iv_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) unsigned int key_offset = key_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) switch (cipher_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) case DRV_CIPHER_ECB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) case DRV_CIPHER_CBC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) case DRV_CIPHER_CBC_CTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) case DRV_CIPHER_CTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) case DRV_CIPHER_OFB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) case DRV_CIPHER_XTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) case DRV_CIPHER_ESSIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (cipher_mode == DRV_CIPHER_ESSIV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) key_len = SHA256_DIGEST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* load XEX key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) hw_desc_init(&desc[*seq_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) set_cipher_mode(&desc[*seq_size], cipher_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) set_cipher_config0(&desc[*seq_size], direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (cc_key_type(tfm) == CC_HW_PROTECTED_KEY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) set_hw_crypto_key(&desc[*seq_size],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ctx_p->hw.key2_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) set_din_type(&desc[*seq_size], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) (key_dma_addr + key_offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) key_len, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) set_xex_data_unit_size(&desc[*seq_size], nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) set_flow_mode(&desc[*seq_size], S_DIN_to_AES2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) set_key_size_aes(&desc[*seq_size], key_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) set_setup_mode(&desc[*seq_size], SETUP_LOAD_XEX_KEY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) (*seq_size)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* Load IV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) hw_desc_init(&desc[*seq_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) set_setup_mode(&desc[*seq_size], SETUP_LOAD_STATE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) set_cipher_mode(&desc[*seq_size], cipher_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) set_cipher_config0(&desc[*seq_size], direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) set_key_size_aes(&desc[*seq_size], key_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) set_flow_mode(&desc[*seq_size], flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) set_din_type(&desc[*seq_size], DMA_DLLI, iv_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) CC_AES_BLOCK_SIZE, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) (*seq_size)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dev_err(dev, "Unsupported cipher mode (%d)\n", cipher_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int cc_out_flow_mode(struct cc_cipher_ctx *ctx_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) switch (ctx_p->flow_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) case S_DIN_to_AES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return DIN_AES_DOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) case S_DIN_to_DES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return DIN_DES_DOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) case S_DIN_to_SM4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return DIN_SM4_DOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return ctx_p->flow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static void cc_setup_key_desc(struct crypto_tfm *tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct cipher_req_ctx *req_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) unsigned int nbytes, struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct device *dev = drvdata_to_dev(ctx_p->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int cipher_mode = ctx_p->cipher_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int flow_mode = ctx_p->flow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) int direction = req_ctx->gen_ctx.op_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dma_addr_t key_dma_addr = ctx_p->user.key_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) unsigned int key_len = ctx_p->keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) unsigned int din_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) switch (cipher_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) case DRV_CIPHER_CBC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) case DRV_CIPHER_CBC_CTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) case DRV_CIPHER_CTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) case DRV_CIPHER_OFB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case DRV_CIPHER_ECB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* Load key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) hw_desc_init(&desc[*seq_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) set_cipher_mode(&desc[*seq_size], cipher_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) set_cipher_config0(&desc[*seq_size], direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (cc_key_type(tfm) == CC_POLICY_PROTECTED_KEY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* We use the AES key size coding for all CPP algs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) set_key_size_aes(&desc[*seq_size], key_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) set_cpp_crypto_key(&desc[*seq_size], ctx_p->cpp.slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) flow_mode = cc_out_flow_mode(ctx_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (flow_mode == S_DIN_to_AES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (cc_key_type(tfm) == CC_HW_PROTECTED_KEY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) set_hw_crypto_key(&desc[*seq_size],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ctx_p->hw.key1_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* CC_POLICY_UNPROTECTED_KEY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * Invalid keys are filtered out in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * sethkey()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) din_size = (key_len == 24) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) AES_MAX_KEY_SIZE : key_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) set_din_type(&desc[*seq_size], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) key_dma_addr, din_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) set_key_size_aes(&desc[*seq_size], key_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /*des*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) set_din_type(&desc[*seq_size], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) key_dma_addr, key_len, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) set_key_size_des(&desc[*seq_size], key_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) set_flow_mode(&desc[*seq_size], flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) (*seq_size)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) case DRV_CIPHER_XTS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) case DRV_CIPHER_ESSIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* Load AES key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) hw_desc_init(&desc[*seq_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) set_cipher_mode(&desc[*seq_size], cipher_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) set_cipher_config0(&desc[*seq_size], direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (cc_key_type(tfm) == CC_HW_PROTECTED_KEY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) set_hw_crypto_key(&desc[*seq_size],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ctx_p->hw.key1_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) set_din_type(&desc[*seq_size], DMA_DLLI, key_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) (key_len / 2), NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) set_key_size_aes(&desc[*seq_size], (key_len / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) set_flow_mode(&desc[*seq_size], flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) (*seq_size)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_err(dev, "Unsupported cipher mode (%d)\n", cipher_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static void cc_setup_mlli_desc(struct crypto_tfm *tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct cipher_req_ctx *req_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct scatterlist *dst, struct scatterlist *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) unsigned int nbytes, void *areq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct cc_hw_desc desc[], unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct device *dev = drvdata_to_dev(ctx_p->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (req_ctx->dma_buf_type == CC_DMA_BUF_MLLI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dev_dbg(dev, " bypass params addr %pad length 0x%X addr 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) &req_ctx->mlli_params.mlli_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) req_ctx->mlli_params.mlli_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ctx_p->drvdata->mlli_sram_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) hw_desc_init(&desc[*seq_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) set_din_type(&desc[*seq_size], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) req_ctx->mlli_params.mlli_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) req_ctx->mlli_params.mlli_len, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) set_dout_sram(&desc[*seq_size],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ctx_p->drvdata->mlli_sram_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) req_ctx->mlli_params.mlli_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) set_flow_mode(&desc[*seq_size], BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) (*seq_size)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static void cc_setup_flow_desc(struct crypto_tfm *tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct cipher_req_ctx *req_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct scatterlist *dst, struct scatterlist *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) unsigned int nbytes, struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct device *dev = drvdata_to_dev(ctx_p->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) unsigned int flow_mode = cc_out_flow_mode(ctx_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) bool last_desc = (ctx_p->key_type == CC_POLICY_PROTECTED_KEY ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ctx_p->cipher_mode == DRV_CIPHER_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* Process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (req_ctx->dma_buf_type == CC_DMA_BUF_DLLI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_dbg(dev, " data params addr %pad length 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) &sg_dma_address(src), nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dev_dbg(dev, " data params addr %pad length 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) &sg_dma_address(dst), nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) hw_desc_init(&desc[*seq_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) set_din_type(&desc[*seq_size], DMA_DLLI, sg_dma_address(src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) nbytes, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) set_dout_dlli(&desc[*seq_size], sg_dma_address(dst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) nbytes, NS_BIT, (!last_desc ? 0 : 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (last_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) set_flow_mode(&desc[*seq_size], flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) (*seq_size)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) hw_desc_init(&desc[*seq_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) set_din_type(&desc[*seq_size], DMA_MLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ctx_p->drvdata->mlli_sram_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) req_ctx->in_mlli_nents, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (req_ctx->out_nents == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dev_dbg(dev, " din/dout params addr 0x%08X addr 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ctx_p->drvdata->mlli_sram_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ctx_p->drvdata->mlli_sram_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) set_dout_mlli(&desc[*seq_size],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ctx_p->drvdata->mlli_sram_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) req_ctx->in_mlli_nents, NS_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) (!last_desc ? 0 : 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dev_dbg(dev, " din/dout params addr 0x%08X addr 0x%08X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ctx_p->drvdata->mlli_sram_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ctx_p->drvdata->mlli_sram_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) (u32)LLI_ENTRY_BYTE_SIZE * req_ctx->in_nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) set_dout_mlli(&desc[*seq_size],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) (ctx_p->drvdata->mlli_sram_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) (LLI_ENTRY_BYTE_SIZE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) req_ctx->in_mlli_nents)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) req_ctx->out_mlli_nents, NS_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) (!last_desc ? 0 : 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (last_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) set_queue_last_ind(ctx_p->drvdata, &desc[*seq_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) set_flow_mode(&desc[*seq_size], flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) (*seq_size)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static void cc_cipher_complete(struct device *dev, void *cc_req, int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct skcipher_request *req = (struct skcipher_request *)cc_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct scatterlist *dst = req->dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct scatterlist *src = req->src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct cipher_req_ctx *req_ctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct crypto_skcipher *sk_tfm = crypto_skcipher_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) unsigned int ivsize = crypto_skcipher_ivsize(sk_tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (err != -EINPROGRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* Not a BACKLOG notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) cc_unmap_cipher_request(dev, req_ctx, ivsize, src, dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) memcpy(req->iv, req_ctx->iv, ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) kfree_sensitive(req_ctx->iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) skcipher_request_complete(req, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static int cc_cipher_process(struct skcipher_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) enum drv_crypto_direction direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct crypto_skcipher *sk_tfm = crypto_skcipher_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct crypto_tfm *tfm = crypto_skcipher_tfm(sk_tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct cipher_req_ctx *req_ctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) unsigned int ivsize = crypto_skcipher_ivsize(sk_tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct scatterlist *dst = req->dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct scatterlist *src = req->src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) unsigned int nbytes = req->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) void *iv = req->iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct device *dev = drvdata_to_dev(ctx_p->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct cc_hw_desc desc[MAX_SKCIPHER_SEQ_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct cc_crypto_req cc_req = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) unsigned int seq_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) gfp_t flags = cc_gfp_flags(&req->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) dev_dbg(dev, "%s req=%p iv=%p nbytes=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ((direction == DRV_CRYPTO_DIRECTION_ENCRYPT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) "Encrypt" : "Decrypt"), req, iv, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* STAT_PHASE_0: Init and sanity checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (validate_data_size(ctx_p, nbytes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) dev_dbg(dev, "Unsupported data size %d.\n", nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) goto exit_process;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (nbytes == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* No data to process is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) goto exit_process;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (ctx_p->fallback_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct skcipher_request *subreq = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) *subreq = *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) skcipher_request_set_tfm(subreq, ctx_p->fallback_tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (direction == DRV_CRYPTO_DIRECTION_ENCRYPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return crypto_skcipher_encrypt(subreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return crypto_skcipher_decrypt(subreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* The IV we are handed may be allocted from the stack so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * we must copy it to a DMAable buffer before use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) req_ctx->iv = kmemdup(iv, ivsize, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!req_ctx->iv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) goto exit_process;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* Setup request structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) cc_req.user_cb = cc_cipher_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) cc_req.user_arg = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* Setup CPP operation details */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (ctx_p->key_type == CC_POLICY_PROTECTED_KEY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) cc_req.cpp.is_cpp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) cc_req.cpp.alg = ctx_p->cpp.alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) cc_req.cpp.slot = ctx_p->cpp.slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* Setup request context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) req_ctx->gen_ctx.op_type = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* STAT_PHASE_1: Map buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) rc = cc_map_cipher_request(ctx_p->drvdata, req_ctx, ivsize, nbytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) req_ctx->iv, src, dst, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev_err(dev, "map_request() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) goto exit_process;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* STAT_PHASE_2: Create sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* Setup state (IV) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) cc_setup_state_desc(tfm, req_ctx, ivsize, nbytes, desc, &seq_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* Setup MLLI line, if needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) cc_setup_mlli_desc(tfm, req_ctx, dst, src, nbytes, req, desc, &seq_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* Setup key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) cc_setup_key_desc(tfm, req_ctx, nbytes, desc, &seq_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* Setup state (IV and XEX key) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) cc_setup_xex_state_desc(tfm, req_ctx, ivsize, nbytes, desc, &seq_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* Data processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) cc_setup_flow_desc(tfm, req_ctx, dst, src, nbytes, desc, &seq_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* Read next IV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) cc_setup_readiv_desc(tfm, req_ctx, ivsize, desc, &seq_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* STAT_PHASE_3: Lock HW and push sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) rc = cc_send_request(ctx_p->drvdata, &cc_req, desc, seq_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) &req->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (rc != -EINPROGRESS && rc != -EBUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* Failed to send the request or request completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * synchronously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) cc_unmap_cipher_request(dev, req_ctx, ivsize, src, dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) exit_process:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (rc != -EINPROGRESS && rc != -EBUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) kfree_sensitive(req_ctx->iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static int cc_cipher_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct cipher_req_ctx *req_ctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) memset(req_ctx, 0, sizeof(*req_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return cc_cipher_process(req, DRV_CRYPTO_DIRECTION_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static int cc_cipher_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct cipher_req_ctx *req_ctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) memset(req_ctx, 0, sizeof(*req_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return cc_cipher_process(req, DRV_CRYPTO_DIRECTION_DECRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* Block cipher alg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static const struct cc_alg_template skcipher_algs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .name = "xts(paes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .driver_name = "xts-paes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .setkey = cc_cipher_sethkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .min_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .max_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .cipher_mode = DRV_CIPHER_XTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .sec_func = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .name = "essiv(cbc(paes),sha256)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .driver_name = "essiv-paes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .setkey = cc_cipher_sethkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .min_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .max_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .cipher_mode = DRV_CIPHER_ESSIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .min_hw_rev = CC_HW_REV_712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .sec_func = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .name = "ecb(paes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .driver_name = "ecb-paes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .setkey = cc_cipher_sethkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .min_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .max_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .ivsize = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .cipher_mode = DRV_CIPHER_ECB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .min_hw_rev = CC_HW_REV_712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .sec_func = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .name = "cbc(paes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .driver_name = "cbc-paes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .setkey = cc_cipher_sethkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .min_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .max_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .cipher_mode = DRV_CIPHER_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .min_hw_rev = CC_HW_REV_712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .sec_func = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .name = "ofb(paes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .driver_name = "ofb-paes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .setkey = cc_cipher_sethkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .min_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .max_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .cipher_mode = DRV_CIPHER_OFB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .min_hw_rev = CC_HW_REV_712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .sec_func = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .name = "cts(cbc(paes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .driver_name = "cts-cbc-paes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .setkey = cc_cipher_sethkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .min_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .max_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .cipher_mode = DRV_CIPHER_CBC_CTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .min_hw_rev = CC_HW_REV_712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .sec_func = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .name = "ctr(paes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .driver_name = "ctr-paes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .setkey = cc_cipher_sethkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .min_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .max_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .cipher_mode = DRV_CIPHER_CTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .min_hw_rev = CC_HW_REV_712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .sec_func = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* See https://www.mail-archive.com/linux-crypto@vger.kernel.org/msg40576.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) * for the reason why this differs from the generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) * implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .name = "xts(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .driver_name = "xts-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .setkey = cc_cipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .min_keysize = AES_MIN_KEY_SIZE * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .max_keysize = AES_MAX_KEY_SIZE * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .cipher_mode = DRV_CIPHER_XTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .name = "essiv(cbc(aes),sha256)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .driver_name = "essiv-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .setkey = cc_cipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .cipher_mode = DRV_CIPHER_ESSIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .min_hw_rev = CC_HW_REV_712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .name = "ecb(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .driver_name = "ecb-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .setkey = cc_cipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .ivsize = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .cipher_mode = DRV_CIPHER_ECB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .name = "cbc(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .driver_name = "cbc-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .setkey = cc_cipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .cipher_mode = DRV_CIPHER_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .name = "ofb(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .driver_name = "ofb-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .setkey = cc_cipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .cipher_mode = DRV_CIPHER_OFB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .name = "cts(cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .driver_name = "cts-cbc-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .setkey = cc_cipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .cipher_mode = DRV_CIPHER_CBC_CTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .name = "ctr(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .driver_name = "ctr-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .setkey = cc_cipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .cipher_mode = DRV_CIPHER_CTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .name = "cbc(des3_ede)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .driver_name = "cbc-3des-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .setkey = cc_cipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .min_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .max_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .cipher_mode = DRV_CIPHER_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .flow_mode = S_DIN_to_DES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .name = "ecb(des3_ede)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .driver_name = "ecb-3des-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .setkey = cc_cipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .min_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .max_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .ivsize = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .cipher_mode = DRV_CIPHER_ECB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .flow_mode = S_DIN_to_DES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .name = "cbc(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .driver_name = "cbc-des-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .setkey = cc_cipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .min_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .max_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .cipher_mode = DRV_CIPHER_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .flow_mode = S_DIN_to_DES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .name = "ecb(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .driver_name = "ecb-des-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .setkey = cc_cipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .min_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .max_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .ivsize = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .cipher_mode = DRV_CIPHER_ECB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .flow_mode = S_DIN_to_DES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .name = "cbc(sm4)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .driver_name = "cbc-sm4-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .blocksize = SM4_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .setkey = cc_cipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .min_keysize = SM4_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .max_keysize = SM4_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .ivsize = SM4_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .cipher_mode = DRV_CIPHER_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .flow_mode = S_DIN_to_SM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .min_hw_rev = CC_HW_REV_713,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .std_body = CC_STD_OSCCA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .name = "ecb(sm4)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .driver_name = "ecb-sm4-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .blocksize = SM4_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .setkey = cc_cipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .min_keysize = SM4_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .max_keysize = SM4_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .ivsize = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .cipher_mode = DRV_CIPHER_ECB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .flow_mode = S_DIN_to_SM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .min_hw_rev = CC_HW_REV_713,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .std_body = CC_STD_OSCCA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .name = "ctr(sm4)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .driver_name = "ctr-sm4-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .setkey = cc_cipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .min_keysize = SM4_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .max_keysize = SM4_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .ivsize = SM4_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .cipher_mode = DRV_CIPHER_CTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .flow_mode = S_DIN_to_SM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .min_hw_rev = CC_HW_REV_713,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .std_body = CC_STD_OSCCA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .name = "cbc(psm4)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .driver_name = "cbc-psm4-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .blocksize = SM4_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .setkey = cc_cipher_sethkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .min_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .max_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .ivsize = SM4_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .cipher_mode = DRV_CIPHER_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .flow_mode = S_DIN_to_SM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .min_hw_rev = CC_HW_REV_713,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .std_body = CC_STD_OSCCA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .sec_func = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .name = "ctr(psm4)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .driver_name = "ctr-psm4-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .blocksize = SM4_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .template_skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .setkey = cc_cipher_sethkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .encrypt = cc_cipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) .decrypt = cc_cipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .min_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .max_keysize = CC_HW_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .ivsize = SM4_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .cipher_mode = DRV_CIPHER_CTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .flow_mode = S_DIN_to_SM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .min_hw_rev = CC_HW_REV_713,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .std_body = CC_STD_OSCCA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .sec_func = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static struct cc_crypto_alg *cc_create_alg(const struct cc_alg_template *tmpl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) struct cc_crypto_alg *t_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) struct skcipher_alg *alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) t_alg = devm_kzalloc(dev, sizeof(*t_alg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (!t_alg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) alg = &t_alg->skcipher_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) memcpy(alg, &tmpl->template_skcipher, sizeof(*alg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) tmpl->driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) alg->base.cra_module = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) alg->base.cra_priority = CC_CRA_PRIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) alg->base.cra_blocksize = tmpl->blocksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) alg->base.cra_alignmask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) alg->base.cra_ctxsize = sizeof(struct cc_cipher_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) alg->base.cra_init = cc_cipher_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) alg->base.cra_exit = cc_cipher_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) t_alg->cipher_mode = tmpl->cipher_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) t_alg->flow_mode = tmpl->flow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) return t_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) int cc_cipher_free(struct cc_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) struct cc_crypto_alg *t_alg, *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /* Remove registered algs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) list_for_each_entry_safe(t_alg, n, &drvdata->alg_list, entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) crypto_unregister_skcipher(&t_alg->skcipher_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) list_del(&t_alg->entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) int cc_cipher_alloc(struct cc_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) struct cc_crypto_alg *t_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) struct device *dev = drvdata_to_dev(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) int rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) int alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) INIT_LIST_HEAD(&drvdata->alg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* Linux crypto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) dev_dbg(dev, "Number of algorithms = %zu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) ARRAY_SIZE(skcipher_algs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) for (alg = 0; alg < ARRAY_SIZE(skcipher_algs); alg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if ((skcipher_algs[alg].min_hw_rev > drvdata->hw_rev) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) !(drvdata->std_bodies & skcipher_algs[alg].std_body) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) (drvdata->sec_disabled && skcipher_algs[alg].sec_func))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) dev_dbg(dev, "creating %s\n", skcipher_algs[alg].driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) t_alg = cc_create_alg(&skcipher_algs[alg], dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (IS_ERR(t_alg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) rc = PTR_ERR(t_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) dev_err(dev, "%s alg allocation failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) skcipher_algs[alg].driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) t_alg->drvdata = drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) dev_dbg(dev, "registering %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) skcipher_algs[alg].driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) rc = crypto_register_skcipher(&t_alg->skcipher_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) dev_dbg(dev, "%s alg registration rc = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) t_alg->skcipher_alg.base.cra_driver_name, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) dev_err(dev, "%s alg registration failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) t_alg->skcipher_alg.base.cra_driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) list_add_tail(&t_alg->entry, &drvdata->alg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) dev_dbg(dev, "Registered %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) t_alg->skcipher_alg.base.cra_driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) cc_cipher_free(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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