^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <crypto/algapi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <crypto/internal/aead.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <crypto/authenc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <crypto/gcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/rtnetlink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <crypto/internal/des.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "cc_driver.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "cc_buffer_mgr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "cc_aead.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "cc_request_mgr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "cc_hash.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "cc_sram_mgr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define template_aead template_u.aead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MAX_AEAD_SETKEY_SEQ 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MAX_AEAD_PROCESS_SEQ 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MAX_HMAC_DIGEST_SIZE (SHA256_DIGEST_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MAX_HMAC_BLOCK_SIZE (SHA256_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MAX_NONCE_SIZE CTR_RFC3686_NONCE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct cc_aead_handle {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 sram_workspace_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct list_head aead_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct cc_hmac_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 *padded_authkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 *ipad_opad; /* IPAD, OPAD*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) dma_addr_t padded_authkey_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) dma_addr_t ipad_opad_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct cc_xcbc_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 *xcbc_keys; /* K1,K2,K3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) dma_addr_t xcbc_keys_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct cc_aead_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct cc_drvdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 ctr_nonce[MAX_NONCE_SIZE]; /* used for ctr3686 iv and aes ccm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u8 *enckey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) dma_addr_t enckey_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct cc_hmac_s hmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct cc_xcbc_s xcbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) } auth_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int enc_keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int auth_keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int authsize; /* Actual (reduced?) size of the MAC/ICv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int hash_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) enum drv_cipher_mode cipher_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) enum cc_flow_mode flow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum drv_hash_mode auth_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void cc_aead_exit(struct crypto_aead *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) dev_dbg(dev, "Clearing context @%p for %s\n", crypto_aead_ctx(tfm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) crypto_tfm_alg_name(&tfm->base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Unmap enckey buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (ctx->enckey) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) dma_free_coherent(dev, AES_MAX_KEY_SIZE, ctx->enckey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ctx->enckey_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) dev_dbg(dev, "Freed enckey DMA buffer enckey_dma_addr=%pad\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) &ctx->enckey_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ctx->enckey_dma_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ctx->enckey = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (ctx->auth_mode == DRV_HASH_XCBC_MAC) { /* XCBC authetication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct cc_xcbc_s *xcbc = &ctx->auth_state.xcbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (xcbc->xcbc_keys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dma_free_coherent(dev, CC_AES_128_BIT_KEY_SIZE * 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) xcbc->xcbc_keys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) xcbc->xcbc_keys_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dev_dbg(dev, "Freed xcbc_keys DMA buffer xcbc_keys_dma_addr=%pad\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) &xcbc->xcbc_keys_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) xcbc->xcbc_keys_dma_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) xcbc->xcbc_keys = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) } else if (ctx->auth_mode != DRV_HASH_NULL) { /* HMAC auth. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct cc_hmac_s *hmac = &ctx->auth_state.hmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (hmac->ipad_opad) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dma_free_coherent(dev, 2 * MAX_HMAC_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) hmac->ipad_opad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) hmac->ipad_opad_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dev_dbg(dev, "Freed ipad_opad DMA buffer ipad_opad_dma_addr=%pad\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) &hmac->ipad_opad_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) hmac->ipad_opad_dma_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) hmac->ipad_opad = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (hmac->padded_authkey) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dma_free_coherent(dev, MAX_HMAC_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) hmac->padded_authkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) hmac->padded_authkey_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dev_dbg(dev, "Freed padded_authkey DMA buffer padded_authkey_dma_addr=%pad\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) &hmac->padded_authkey_dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) hmac->padded_authkey_dma_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) hmac->padded_authkey = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static unsigned int cc_get_aead_hash_len(struct crypto_aead *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return cc_get_default_hash_len(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int cc_aead_init(struct crypto_aead *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct aead_alg *alg = crypto_aead_alg(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct cc_crypto_alg *cc_alg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) container_of(alg, struct cc_crypto_alg, aead_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct device *dev = drvdata_to_dev(cc_alg->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) dev_dbg(dev, "Initializing context @%p for %s\n", ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) crypto_tfm_alg_name(&tfm->base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Initialize modes in instance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ctx->cipher_mode = cc_alg->cipher_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ctx->flow_mode = cc_alg->flow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ctx->auth_mode = cc_alg->auth_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ctx->drvdata = cc_alg->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) crypto_aead_set_reqsize(tfm, sizeof(struct aead_req_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Allocate key buffer, cache line aligned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ctx->enckey = dma_alloc_coherent(dev, AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) &ctx->enckey_dma_addr, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (!ctx->enckey) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev_err(dev, "Failed allocating key buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) goto init_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev_dbg(dev, "Allocated enckey buffer in context ctx->enckey=@%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ctx->enckey);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Set default authlen value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ctx->auth_mode == DRV_HASH_XCBC_MAC) { /* XCBC authetication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct cc_xcbc_s *xcbc = &ctx->auth_state.xcbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) const unsigned int key_size = CC_AES_128_BIT_KEY_SIZE * 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Allocate dma-coherent buffer for XCBC's K1+K2+K3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* (and temporary for user key - up to 256b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) xcbc->xcbc_keys = dma_alloc_coherent(dev, key_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) &xcbc->xcbc_keys_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!xcbc->xcbc_keys) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) dev_err(dev, "Failed allocating buffer for XCBC keys\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) goto init_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) } else if (ctx->auth_mode != DRV_HASH_NULL) { /* HMAC authentication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct cc_hmac_s *hmac = &ctx->auth_state.hmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const unsigned int digest_size = 2 * MAX_HMAC_DIGEST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) dma_addr_t *pkey_dma = &hmac->padded_authkey_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Allocate dma-coherent buffer for IPAD + OPAD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) hmac->ipad_opad = dma_alloc_coherent(dev, digest_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) &hmac->ipad_opad_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!hmac->ipad_opad) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_err(dev, "Failed allocating IPAD/OPAD buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) goto init_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_dbg(dev, "Allocated authkey buffer in context ctx->authkey=@%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) hmac->ipad_opad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) hmac->padded_authkey = dma_alloc_coherent(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MAX_HMAC_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pkey_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!hmac->padded_authkey) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_err(dev, "failed to allocate padded_authkey\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) goto init_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ctx->auth_state.hmac.ipad_opad = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ctx->auth_state.hmac.padded_authkey = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ctx->hash_len = cc_get_aead_hash_len(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) init_failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) cc_aead_exit(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void cc_aead_complete(struct device *dev, void *cc_req, int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct aead_request *areq = (struct aead_request *)cc_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct aead_req_ctx *areq_ctx = aead_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct crypto_aead *tfm = crypto_aead_reqtfm(cc_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* BACKLOG notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (err == -EINPROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) cc_unmap_aead_request(dev, areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Restore ordinary iv pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) areq->iv = areq_ctx->backup_iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (memcmp(areq_ctx->mac_buf, areq_ctx->icv_virt_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ctx->authsize) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_dbg(dev, "Payload authentication failure, (auth-size=%d, cipher=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ctx->authsize, ctx->cipher_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* In case of payload authentication failure, MUST NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * revealed the decrypted message --> zero its memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) sg_zero_buffer(areq->dst, sg_nents(areq->dst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) areq->cryptlen, areq->assoclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) err = -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*ENCRYPT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) } else if (areq_ctx->is_icv_fragmented) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 skip = areq->cryptlen + areq_ctx->dst_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) cc_copy_sg_portion(dev, areq_ctx->mac_buf, areq_ctx->dst_sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) skip, (skip + ctx->authsize),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) CC_SG_FROM_BUF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) aead_request_complete(areq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static unsigned int xcbc_setkey(struct cc_hw_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct cc_aead_ctx *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Load the AES key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) hw_desc_init(&desc[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* We are using for the source/user key the same buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * as for the output keys, * because after this key loading it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * is not needed anymore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) set_din_type(&desc[0], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ctx->auth_state.xcbc.xcbc_keys_dma_addr, ctx->auth_keylen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) set_cipher_mode(&desc[0], DRV_CIPHER_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) set_cipher_config0(&desc[0], DRV_CRYPTO_DIRECTION_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) set_key_size_aes(&desc[0], ctx->auth_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) set_flow_mode(&desc[0], S_DIN_to_AES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) set_setup_mode(&desc[0], SETUP_LOAD_KEY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) hw_desc_init(&desc[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) set_din_const(&desc[1], 0x01010101, CC_AES_128_BIT_KEY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) set_flow_mode(&desc[1], DIN_AES_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) set_dout_dlli(&desc[1], ctx->auth_state.xcbc.xcbc_keys_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) AES_KEYSIZE_128, NS_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) hw_desc_init(&desc[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) set_din_const(&desc[2], 0x02020202, CC_AES_128_BIT_KEY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) set_flow_mode(&desc[2], DIN_AES_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) set_dout_dlli(&desc[2], (ctx->auth_state.xcbc.xcbc_keys_dma_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) + AES_KEYSIZE_128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) AES_KEYSIZE_128, NS_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) hw_desc_init(&desc[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) set_din_const(&desc[3], 0x03030303, CC_AES_128_BIT_KEY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) set_flow_mode(&desc[3], DIN_AES_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) set_dout_dlli(&desc[3], (ctx->auth_state.xcbc.xcbc_keys_dma_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) + 2 * AES_KEYSIZE_128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) AES_KEYSIZE_128, NS_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static unsigned int hmac_setkey(struct cc_hw_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct cc_aead_ctx *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int hmac_pad_const[2] = { HMAC_IPAD_CONST, HMAC_OPAD_CONST };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned int digest_ofs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned int hash_mode = (ctx->auth_mode == DRV_HASH_SHA1) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) DRV_HASH_HW_SHA1 : DRV_HASH_HW_SHA256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int digest_size = (ctx->auth_mode == DRV_HASH_SHA1) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) CC_SHA1_DIGEST_SIZE : CC_SHA256_DIGEST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct cc_hmac_s *hmac = &ctx->auth_state.hmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* calc derived HMAC key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Load hash initial state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) set_cipher_mode(&desc[idx], hash_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) set_din_sram(&desc[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) cc_larval_digest_addr(ctx->drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ctx->auth_mode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) digest_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Load the hash current length*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) set_cipher_mode(&desc[idx], hash_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) set_din_const(&desc[idx], 0, ctx->hash_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Prepare ipad key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) set_xor_val(&desc[idx], hmac_pad_const[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) set_cipher_mode(&desc[idx], hash_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) set_setup_mode(&desc[idx], SETUP_LOAD_STATE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Perform HASH update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) set_din_type(&desc[idx], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) hmac->padded_authkey_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) SHA256_BLOCK_SIZE, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) set_cipher_mode(&desc[idx], hash_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) set_xor_active(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) set_flow_mode(&desc[idx], DIN_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Get the digset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) set_cipher_mode(&desc[idx], hash_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) set_dout_dlli(&desc[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) (hmac->ipad_opad_dma_addr + digest_ofs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) digest_size, NS_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) set_flow_mode(&desc[idx], S_HASH_to_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) digest_ofs += digest_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int validate_keys_sizes(struct cc_aead_ctx *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_dbg(dev, "enc_keylen=%u authkeylen=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ctx->enc_keylen, ctx->auth_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) switch (ctx->auth_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) case DRV_HASH_SHA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case DRV_HASH_SHA256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case DRV_HASH_XCBC_MAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (ctx->auth_keylen != AES_KEYSIZE_128 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ctx->auth_keylen != AES_KEYSIZE_192 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ctx->auth_keylen != AES_KEYSIZE_256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case DRV_HASH_NULL: /* Not authenc (e.g., CCM) - no auth_key) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (ctx->auth_keylen > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dev_dbg(dev, "Invalid auth_mode=%d\n", ctx->auth_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Check cipher key size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (ctx->flow_mode == S_DIN_to_DES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ctx->enc_keylen != DES3_EDE_KEY_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_dbg(dev, "Invalid cipher(3DES) key size: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ctx->enc_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) } else { /* Default assumed to be AES ciphers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ctx->enc_keylen != AES_KEYSIZE_128 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ctx->enc_keylen != AES_KEYSIZE_192 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ctx->enc_keylen != AES_KEYSIZE_256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_dbg(dev, "Invalid cipher(AES) key size: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ctx->enc_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0; /* All tests of keys sizes passed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* This function prepers the user key so it can pass to the hmac processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * (copy to intenral buffer or hash in case of key longer than block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int cc_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *authkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dma_addr_t key_dma_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u32 larval_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct cc_crypto_req cc_req = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unsigned int blocksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned int digestsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned int hashmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u8 *key = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct cc_hw_desc desc[MAX_AEAD_SETKEY_SEQ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dma_addr_t padded_authkey_dma_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ctx->auth_state.hmac.padded_authkey_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) switch (ctx->auth_mode) { /* auth_key required and >0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case DRV_HASH_SHA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) blocksize = SHA1_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) digestsize = SHA1_DIGEST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) hashmode = DRV_HASH_HW_SHA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case DRV_HASH_SHA256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) blocksize = SHA256_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) digestsize = SHA256_DIGEST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) hashmode = DRV_HASH_HW_SHA256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (keylen != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) key = kmemdup(authkey, keylen, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!key)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) key_dma_addr = dma_map_single(dev, key, keylen, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (dma_mapping_error(dev, key_dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dev_err(dev, "Mapping key va=0x%p len=%u for DMA failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) kfree_sensitive(key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (keylen > blocksize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* Load hash initial state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) set_cipher_mode(&desc[idx], hashmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) larval_addr = cc_larval_digest_addr(ctx->drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ctx->auth_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) set_din_sram(&desc[idx], larval_addr, digestsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* Load the hash current length*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) set_cipher_mode(&desc[idx], hashmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) set_din_const(&desc[idx], 0, ctx->hash_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) set_din_type(&desc[idx], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) key_dma_addr, keylen, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) set_flow_mode(&desc[idx], DIN_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Get hashed key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) set_cipher_mode(&desc[idx], hashmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) set_dout_dlli(&desc[idx], padded_authkey_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) digestsize, NS_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) set_flow_mode(&desc[idx], S_HASH_to_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) set_cipher_config0(&desc[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) HASH_DIGEST_RESULT_LITTLE_ENDIAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) set_din_const(&desc[idx], 0, (blocksize - digestsize));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) set_flow_mode(&desc[idx], BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) set_dout_dlli(&desc[idx], (padded_authkey_dma_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) digestsize), (blocksize - digestsize),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) NS_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) set_din_type(&desc[idx], DMA_DLLI, key_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) keylen, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) set_flow_mode(&desc[idx], BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) set_dout_dlli(&desc[idx], padded_authkey_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) keylen, NS_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if ((blocksize - keylen) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) set_din_const(&desc[idx], 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) (blocksize - keylen));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) set_flow_mode(&desc[idx], BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) set_dout_dlli(&desc[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) (padded_authkey_dma_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) keylen),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) (blocksize - keylen), NS_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) set_din_const(&desc[idx], 0, (blocksize - keylen));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) set_flow_mode(&desc[idx], BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) set_dout_dlli(&desc[idx], padded_authkey_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) blocksize, NS_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) rc = cc_send_sync_request(ctx->drvdata, &cc_req, desc, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_err(dev, "send_request() failed (rc=%d)\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (key_dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) dma_unmap_single(dev, key_dma_addr, keylen, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) kfree_sensitive(key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int cc_aead_setkey(struct crypto_aead *tfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct cc_crypto_req cc_req = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct cc_hw_desc desc[MAX_AEAD_SETKEY_SEQ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) unsigned int seq_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) const u8 *enckey, *authkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_dbg(dev, "Setting key in context @%p for %s. key=%p keylen=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ctx, crypto_tfm_alg_name(crypto_aead_tfm(tfm)), key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* STAT_PHASE_0: Init and sanity checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (ctx->auth_mode != DRV_HASH_NULL) { /* authenc() alg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct crypto_authenc_keys keys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) rc = crypto_authenc_extractkeys(&keys, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) enckey = keys.enckey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) authkey = keys.authkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ctx->enc_keylen = keys.enckeylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ctx->auth_keylen = keys.authkeylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (ctx->cipher_mode == DRV_CIPHER_CTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* the nonce is stored in bytes at end of key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (ctx->enc_keylen <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) (AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Copy nonce from last 4 bytes in CTR key to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * first 4 bytes in CTR IV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) memcpy(ctx->ctr_nonce, enckey + ctx->enc_keylen -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) CTR_RFC3686_NONCE_SIZE, CTR_RFC3686_NONCE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* Set CTR key size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ctx->enc_keylen -= CTR_RFC3686_NONCE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) } else { /* non-authenc - has just one key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) enckey = key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) authkey = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ctx->enc_keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ctx->auth_keylen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) rc = validate_keys_sizes(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* STAT_PHASE_1: Copy key to ctx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Get key material */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) memcpy(ctx->enckey, enckey, ctx->enc_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (ctx->enc_keylen == 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) memset(ctx->enckey + 24, 0, CC_AES_KEY_SIZE_MAX - 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (ctx->auth_mode == DRV_HASH_XCBC_MAC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) memcpy(ctx->auth_state.xcbc.xcbc_keys, authkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ctx->auth_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) } else if (ctx->auth_mode != DRV_HASH_NULL) { /* HMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) rc = cc_get_plain_hmac_key(tfm, authkey, ctx->auth_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* STAT_PHASE_2: Create sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) switch (ctx->auth_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) case DRV_HASH_SHA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) case DRV_HASH_SHA256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) seq_len = hmac_setkey(desc, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case DRV_HASH_XCBC_MAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) seq_len = xcbc_setkey(desc, ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) case DRV_HASH_NULL: /* non-authenc modes, e.g., CCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) break; /* No auth. key setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_err(dev, "Unsupported authenc (%d)\n", ctx->auth_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* STAT_PHASE_3: Submit sequence to HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (seq_len > 0) { /* For CCM there is no sequence to setup the key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) rc = cc_send_sync_request(ctx->drvdata, &cc_req, desc, seq_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dev_err(dev, "send_request() failed (rc=%d)\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Update STAT_PHASE_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static int cc_des3_aead_setkey(struct crypto_aead *aead, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct crypto_authenc_keys keys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) err = crypto_authenc_extractkeys(&keys, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (unlikely(err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) err = verify_aead_des3_key(aead, keys.enckey, keys.enckeylen) ?:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) cc_aead_setkey(aead, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) memzero_explicit(&keys, sizeof(keys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static int cc_rfc4309_ccm_setkey(struct crypto_aead *tfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (keylen < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) keylen -= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) memcpy(ctx->ctr_nonce, key + keylen, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return cc_aead_setkey(tfm, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static int cc_aead_setauthsize(struct crypto_aead *authenc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct cc_aead_ctx *ctx = crypto_aead_ctx(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* Unsupported auth. sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (authsize == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) authsize > crypto_aead_maxauthsize(authenc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ctx->authsize = authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dev_dbg(dev, "authlen=%d\n", ctx->authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int cc_rfc4309_ccm_setauthsize(struct crypto_aead *authenc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) switch (authsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return cc_aead_setauthsize(authenc, authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int cc_ccm_setauthsize(struct crypto_aead *authenc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) switch (authsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) case 14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return cc_aead_setauthsize(authenc, authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static void cc_set_assoc_desc(struct aead_request *areq, unsigned int flow_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct cc_hw_desc desc[], unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct crypto_aead *tfm = crypto_aead_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct aead_req_ctx *areq_ctx = aead_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) enum cc_req_dma_buf_type assoc_dma_type = areq_ctx->assoc_buff_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) unsigned int idx = *seq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) switch (assoc_dma_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) case CC_DMA_BUF_DLLI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_dbg(dev, "ASSOC buffer type DLLI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) set_din_type(&desc[idx], DMA_DLLI, sg_dma_address(areq->src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) areq_ctx->assoclen, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) set_flow_mode(&desc[idx], flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (ctx->auth_mode == DRV_HASH_XCBC_MAC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) areq_ctx->cryptlen > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) set_din_not_last_indication(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) case CC_DMA_BUF_MLLI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dev_dbg(dev, "ASSOC buffer type MLLI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) set_din_type(&desc[idx], DMA_MLLI, areq_ctx->assoc.sram_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) areq_ctx->assoc.mlli_nents, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) set_flow_mode(&desc[idx], flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (ctx->auth_mode == DRV_HASH_XCBC_MAC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) areq_ctx->cryptlen > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) set_din_not_last_indication(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) case CC_DMA_BUF_NULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dev_err(dev, "Invalid ASSOC buffer type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) *seq_size = (++idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static void cc_proc_authen_desc(struct aead_request *areq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) unsigned int flow_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) unsigned int *seq_size, int direct)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct aead_req_ctx *areq_ctx = aead_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) enum cc_req_dma_buf_type data_dma_type = areq_ctx->data_buff_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) unsigned int idx = *seq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct crypto_aead *tfm = crypto_aead_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) switch (data_dma_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) case CC_DMA_BUF_DLLI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct scatterlist *cipher =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) areq_ctx->dst_sgl : areq_ctx->src_sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) unsigned int offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) areq_ctx->dst_offset : areq_ctx->src_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) dev_dbg(dev, "AUTHENC: SRC/DST buffer type DLLI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) set_din_type(&desc[idx], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) (sg_dma_address(cipher) + offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) areq_ctx->cryptlen, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) set_flow_mode(&desc[idx], flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) case CC_DMA_BUF_MLLI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* DOUBLE-PASS flow (as default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * assoc. + iv + data -compact in one table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * if assoclen is ZERO only IV perform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u32 mlli_addr = areq_ctx->assoc.sram_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u32 mlli_nents = areq_ctx->assoc.mlli_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (areq_ctx->is_single_pass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) mlli_addr = areq_ctx->dst.sram_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) mlli_nents = areq_ctx->dst.mlli_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) mlli_addr = areq_ctx->src.sram_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) mlli_nents = areq_ctx->src.mlli_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dev_dbg(dev, "AUTHENC: SRC/DST buffer type MLLI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) set_din_type(&desc[idx], DMA_MLLI, mlli_addr, mlli_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) set_flow_mode(&desc[idx], flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) case CC_DMA_BUF_NULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dev_err(dev, "AUTHENC: Invalid SRC/DST buffer type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) *seq_size = (++idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static void cc_proc_cipher_desc(struct aead_request *areq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) unsigned int flow_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) unsigned int idx = *seq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct aead_req_ctx *areq_ctx = aead_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) enum cc_req_dma_buf_type data_dma_type = areq_ctx->data_buff_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct crypto_aead *tfm = crypto_aead_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (areq_ctx->cryptlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return; /*null processing*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) switch (data_dma_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) case CC_DMA_BUF_DLLI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dev_dbg(dev, "CIPHER: SRC/DST buffer type DLLI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) set_din_type(&desc[idx], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) (sg_dma_address(areq_ctx->src_sgl) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) areq_ctx->src_offset), areq_ctx->cryptlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) set_dout_dlli(&desc[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) (sg_dma_address(areq_ctx->dst_sgl) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) areq_ctx->dst_offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) areq_ctx->cryptlen, NS_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) set_flow_mode(&desc[idx], flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) case CC_DMA_BUF_MLLI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) dev_dbg(dev, "CIPHER: SRC/DST buffer type MLLI\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) set_din_type(&desc[idx], DMA_MLLI, areq_ctx->src.sram_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) areq_ctx->src.mlli_nents, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) set_dout_mlli(&desc[idx], areq_ctx->dst.sram_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) areq_ctx->dst.mlli_nents, NS_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) set_flow_mode(&desc[idx], flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) case CC_DMA_BUF_NULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) dev_err(dev, "CIPHER: Invalid SRC/DST buffer type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) *seq_size = (++idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static void cc_proc_digest_desc(struct aead_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct aead_req_ctx *req_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) unsigned int idx = *seq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) unsigned int hash_mode = (ctx->auth_mode == DRV_HASH_SHA1) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) DRV_HASH_HW_SHA1 : DRV_HASH_HW_SHA256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) int direct = req_ctx->gen_ctx.op_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* Get final ICV result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) set_flow_mode(&desc[idx], S_HASH_to_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) set_dout_dlli(&desc[idx], req_ctx->icv_dma_addr, ctx->authsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) NS_BIT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) set_queue_last_ind(ctx->drvdata, &desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (ctx->auth_mode == DRV_HASH_XCBC_MAC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) set_aes_not_hash_mode(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) set_cipher_config0(&desc[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) HASH_DIGEST_RESULT_LITTLE_ENDIAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) set_cipher_mode(&desc[idx], hash_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) } else { /*Decrypt*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* Get ICV out from hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) set_flow_mode(&desc[idx], S_HASH_to_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) set_dout_dlli(&desc[idx], req_ctx->mac_buf_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ctx->authsize, NS_BIT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) set_queue_last_ind(ctx->drvdata, &desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) set_cipher_config0(&desc[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) HASH_DIGEST_RESULT_LITTLE_ENDIAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) set_cipher_config1(&desc[idx], HASH_PADDING_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (ctx->auth_mode == DRV_HASH_XCBC_MAC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) set_aes_not_hash_mode(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) set_cipher_mode(&desc[idx], hash_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) *seq_size = (++idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static void cc_set_cipher_desc(struct aead_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct aead_req_ctx *req_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) unsigned int hw_iv_size = req_ctx->hw_iv_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) unsigned int idx = *seq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) int direct = req_ctx->gen_ctx.op_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* Setup cipher state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) set_cipher_config0(&desc[idx], direct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) set_flow_mode(&desc[idx], ctx->flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) set_din_type(&desc[idx], DMA_DLLI, req_ctx->gen_ctx.iv_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) hw_iv_size, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (ctx->cipher_mode == DRV_CIPHER_CTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) set_setup_mode(&desc[idx], SETUP_LOAD_STATE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) set_cipher_mode(&desc[idx], ctx->cipher_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* Setup enc. key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) set_cipher_config0(&desc[idx], direct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) set_flow_mode(&desc[idx], ctx->flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (ctx->flow_mode == S_DIN_to_AES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) set_din_type(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ((ctx->enc_keylen == 24) ? CC_AES_KEY_SIZE_MAX :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ctx->enc_keylen), NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) set_key_size_aes(&desc[idx], ctx->enc_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) set_din_type(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ctx->enc_keylen, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) set_key_size_des(&desc[idx], ctx->enc_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) set_cipher_mode(&desc[idx], ctx->cipher_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) *seq_size = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static void cc_proc_cipher(struct aead_request *req, struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) unsigned int *seq_size, unsigned int data_flow_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct aead_req_ctx *req_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) int direct = req_ctx->gen_ctx.op_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) unsigned int idx = *seq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (req_ctx->cryptlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return; /*null processing*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) cc_set_cipher_desc(req, desc, &idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) cc_proc_cipher_desc(req, data_flow_mode, desc, &idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* We must wait for DMA to write all cipher */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) set_din_no_dma(&desc[idx], 0, 0xfffff0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) set_dout_no_dma(&desc[idx], 0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) *seq_size = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static void cc_set_hmac_desc(struct aead_request *req, struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) unsigned int hash_mode = (ctx->auth_mode == DRV_HASH_SHA1) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) DRV_HASH_HW_SHA1 : DRV_HASH_HW_SHA256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) unsigned int digest_size = (ctx->auth_mode == DRV_HASH_SHA1) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) CC_SHA1_DIGEST_SIZE : CC_SHA256_DIGEST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) unsigned int idx = *seq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* Loading hash ipad xor key state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) set_cipher_mode(&desc[idx], hash_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) set_din_type(&desc[idx], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ctx->auth_state.hmac.ipad_opad_dma_addr, digest_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* Load init. digest len (64 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) set_cipher_mode(&desc[idx], hash_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) set_din_sram(&desc[idx], cc_digest_len_addr(ctx->drvdata, hash_mode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ctx->hash_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) *seq_size = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static void cc_set_xcbc_desc(struct aead_request *req, struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) unsigned int idx = *seq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* Loading MAC state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) set_din_const(&desc[idx], 0, CC_AES_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) set_aes_not_hash_mode(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /* Setup XCBC MAC K1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) set_din_type(&desc[idx], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ctx->auth_state.xcbc.xcbc_keys_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) AES_KEYSIZE_128, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) set_aes_not_hash_mode(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* Setup XCBC MAC K2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) set_din_type(&desc[idx], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) (ctx->auth_state.xcbc.xcbc_keys_dma_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) AES_KEYSIZE_128), AES_KEYSIZE_128, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) set_setup_mode(&desc[idx], SETUP_LOAD_STATE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) set_aes_not_hash_mode(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* Setup XCBC MAC K3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) set_din_type(&desc[idx], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) (ctx->auth_state.xcbc.xcbc_keys_dma_addr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) 2 * AES_KEYSIZE_128), AES_KEYSIZE_128, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) set_setup_mode(&desc[idx], SETUP_LOAD_STATE2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) set_cipher_mode(&desc[idx], DRV_CIPHER_XCBC_MAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) set_key_size_aes(&desc[idx], CC_AES_128_BIT_KEY_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) set_aes_not_hash_mode(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) *seq_size = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static void cc_proc_header_desc(struct aead_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) unsigned int idx = *seq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /* Hash associated data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (areq_ctx->assoclen > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) cc_set_assoc_desc(req, DIN_HASH, desc, &idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* Hash IV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) *seq_size = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static void cc_proc_scheme_desc(struct aead_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) struct cc_aead_handle *aead_handle = ctx->drvdata->aead_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) unsigned int hash_mode = (ctx->auth_mode == DRV_HASH_SHA1) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) DRV_HASH_HW_SHA1 : DRV_HASH_HW_SHA256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) unsigned int digest_size = (ctx->auth_mode == DRV_HASH_SHA1) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) CC_SHA1_DIGEST_SIZE : CC_SHA256_DIGEST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) unsigned int idx = *seq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) set_cipher_mode(&desc[idx], hash_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) set_dout_sram(&desc[idx], aead_handle->sram_workspace_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ctx->hash_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) set_flow_mode(&desc[idx], S_HASH_to_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) set_setup_mode(&desc[idx], SETUP_WRITE_STATE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) set_cipher_do(&desc[idx], DO_PAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* Get final ICV result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) set_dout_sram(&desc[idx], aead_handle->sram_workspace_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) digest_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) set_flow_mode(&desc[idx], S_HASH_to_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) set_cipher_config0(&desc[idx], HASH_DIGEST_RESULT_LITTLE_ENDIAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) set_cipher_mode(&desc[idx], hash_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* Loading hash opad xor key state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) set_cipher_mode(&desc[idx], hash_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) set_din_type(&desc[idx], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) (ctx->auth_state.hmac.ipad_opad_dma_addr + digest_size),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) digest_size, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) /* Load init. digest len (64 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) set_cipher_mode(&desc[idx], hash_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) set_din_sram(&desc[idx], cc_digest_len_addr(ctx->drvdata, hash_mode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) ctx->hash_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* Perform HASH update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) set_din_sram(&desc[idx], aead_handle->sram_workspace_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) digest_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) set_flow_mode(&desc[idx], DIN_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) *seq_size = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static void cc_mlli_to_sram(struct aead_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct cc_hw_desc desc[], unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct aead_req_ctx *req_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if ((req_ctx->assoc_buff_type == CC_DMA_BUF_MLLI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) req_ctx->data_buff_type == CC_DMA_BUF_MLLI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) !req_ctx->is_single_pass) && req_ctx->mlli_params.mlli_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) dev_dbg(dev, "Copy-to-sram: mlli_dma=%08x, mlli_size=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) ctx->drvdata->mlli_sram_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) req_ctx->mlli_params.mlli_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* Copy MLLI table host-to-sram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) hw_desc_init(&desc[*seq_size]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) set_din_type(&desc[*seq_size], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) req_ctx->mlli_params.mlli_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) req_ctx->mlli_params.mlli_len, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) set_dout_sram(&desc[*seq_size],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ctx->drvdata->mlli_sram_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) req_ctx->mlli_params.mlli_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) set_flow_mode(&desc[*seq_size], BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) (*seq_size)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static enum cc_flow_mode cc_get_data_flow(enum drv_crypto_direction direct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) enum cc_flow_mode setup_flow_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) bool is_single_pass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) enum cc_flow_mode data_flow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (setup_flow_mode == S_DIN_to_AES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) data_flow_mode = is_single_pass ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) AES_to_HASH_and_DOUT : DIN_AES_DOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) data_flow_mode = is_single_pass ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) DES_to_HASH_and_DOUT : DIN_DES_DOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) } else { /* Decrypt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (setup_flow_mode == S_DIN_to_AES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) data_flow_mode = is_single_pass ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) AES_and_HASH : DIN_AES_DOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) data_flow_mode = is_single_pass ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) DES_and_HASH : DIN_DES_DOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return data_flow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static void cc_hmac_authenc(struct aead_request *req, struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) struct aead_req_ctx *req_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) int direct = req_ctx->gen_ctx.op_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) unsigned int data_flow_mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) cc_get_data_flow(direct, ctx->flow_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) req_ctx->is_single_pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (req_ctx->is_single_pass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * Single-pass flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) cc_set_hmac_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) cc_set_cipher_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) cc_proc_header_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) cc_proc_cipher_desc(req, data_flow_mode, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) cc_proc_scheme_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) cc_proc_digest_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * Double-pass flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * Fallback for unsupported single-pass modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * i.e. using assoc. data of non-word-multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* encrypt first.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) cc_proc_cipher(req, desc, seq_size, data_flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /* authenc after..*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) cc_set_hmac_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) cc_proc_authen_desc(req, DIN_HASH, desc, seq_size, direct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) cc_proc_scheme_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) cc_proc_digest_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) } else { /*DECRYPT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /* authenc first..*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) cc_set_hmac_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) cc_proc_authen_desc(req, DIN_HASH, desc, seq_size, direct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) cc_proc_scheme_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /* decrypt after.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) cc_proc_cipher(req, desc, seq_size, data_flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /* read the digest result with setting the completion bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * must be after the cipher operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) cc_proc_digest_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) cc_xcbc_authenc(struct aead_request *req, struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct aead_req_ctx *req_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) int direct = req_ctx->gen_ctx.op_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) unsigned int data_flow_mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) cc_get_data_flow(direct, ctx->flow_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) req_ctx->is_single_pass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (req_ctx->is_single_pass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) * Single-pass flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) cc_set_xcbc_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) cc_set_cipher_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) cc_proc_header_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) cc_proc_cipher_desc(req, data_flow_mode, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) cc_proc_digest_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * Double-pass flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * Fallback for unsupported single-pass modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * i.e. using assoc. data of non-word-multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /* encrypt first.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) cc_proc_cipher(req, desc, seq_size, data_flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /* authenc after.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) cc_set_xcbc_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) cc_proc_authen_desc(req, DIN_HASH, desc, seq_size, direct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) cc_proc_digest_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) } else { /*DECRYPT*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /* authenc first.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) cc_set_xcbc_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) cc_proc_authen_desc(req, DIN_HASH, desc, seq_size, direct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /* decrypt after..*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) cc_proc_cipher(req, desc, seq_size, data_flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /* read the digest result with setting the completion bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) * must be after the cipher operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) cc_proc_digest_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static int validate_data_size(struct cc_aead_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) enum drv_crypto_direction direct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) unsigned int assoclen = areq_ctx->assoclen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) unsigned int cipherlen = (direct == DRV_CRYPTO_DIRECTION_DECRYPT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) (req->cryptlen - ctx->authsize) : req->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (direct == DRV_CRYPTO_DIRECTION_DECRYPT &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) req->cryptlen < ctx->authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) goto data_size_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) areq_ctx->is_single_pass = true; /*defaulted to fast flow*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) switch (ctx->flow_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) case S_DIN_to_AES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (ctx->cipher_mode == DRV_CIPHER_CBC &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) !IS_ALIGNED(cipherlen, AES_BLOCK_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) goto data_size_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (ctx->cipher_mode == DRV_CIPHER_CCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (ctx->cipher_mode == DRV_CIPHER_GCTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (areq_ctx->plaintext_authenticate_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) areq_ctx->is_single_pass = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (!IS_ALIGNED(assoclen, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) areq_ctx->is_single_pass = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (ctx->cipher_mode == DRV_CIPHER_CTR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) !IS_ALIGNED(cipherlen, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) areq_ctx->is_single_pass = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) case S_DIN_to_DES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (!IS_ALIGNED(cipherlen, DES_BLOCK_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) goto data_size_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (!IS_ALIGNED(assoclen, DES_BLOCK_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) areq_ctx->is_single_pass = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) dev_err(dev, "Unexpected flow mode (%d)\n", ctx->flow_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) goto data_size_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) data_size_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static unsigned int format_ccm_a0(u8 *pa0_buff, u32 header_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) unsigned int len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (header_size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (header_size < ((1UL << 16) - (1UL << 8))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) pa0_buff[0] = (header_size >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) pa0_buff[1] = header_size & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) len = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) pa0_buff[0] = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) pa0_buff[1] = 0xFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) pa0_buff[2] = (header_size >> 24) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) pa0_buff[3] = (header_size >> 16) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) pa0_buff[4] = (header_size >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) pa0_buff[5] = header_size & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static int set_msg_len(u8 *block, unsigned int msglen, unsigned int csize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) __be32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) memset(block, 0, csize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) block += csize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (csize >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) csize = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) else if (msglen > (1 << (8 * csize)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return -EOVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) data = cpu_to_be32(msglen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) memcpy(block - csize, (u8 *)&data + 4 - csize, csize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) static int cc_ccm(struct aead_request *req, struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) struct aead_req_ctx *req_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) unsigned int idx = *seq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) unsigned int cipher_flow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) dma_addr_t mac_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (req_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) cipher_flow_mode = AES_to_HASH_and_DOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) mac_result = req_ctx->mac_buf_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) } else { /* Encrypt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) cipher_flow_mode = AES_and_HASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) mac_result = req_ctx->icv_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) /* load key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) set_cipher_mode(&desc[idx], DRV_CIPHER_CTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) set_din_type(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) ((ctx->enc_keylen == 24) ? CC_AES_KEY_SIZE_MAX :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) ctx->enc_keylen), NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) set_key_size_aes(&desc[idx], ctx->enc_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) set_flow_mode(&desc[idx], S_DIN_to_AES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /* load ctr state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) set_cipher_mode(&desc[idx], DRV_CIPHER_CTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) set_key_size_aes(&desc[idx], ctx->enc_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) set_din_type(&desc[idx], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) req_ctx->gen_ctx.iv_dma_addr, AES_BLOCK_SIZE, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) set_setup_mode(&desc[idx], SETUP_LOAD_STATE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) set_flow_mode(&desc[idx], S_DIN_to_AES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /* load MAC key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) set_cipher_mode(&desc[idx], DRV_CIPHER_CBC_MAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) set_din_type(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) ((ctx->enc_keylen == 24) ? CC_AES_KEY_SIZE_MAX :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) ctx->enc_keylen), NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) set_key_size_aes(&desc[idx], ctx->enc_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) set_aes_not_hash_mode(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* load MAC state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) set_cipher_mode(&desc[idx], DRV_CIPHER_CBC_MAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) set_key_size_aes(&desc[idx], ctx->enc_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) set_din_type(&desc[idx], DMA_DLLI, req_ctx->mac_buf_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) AES_BLOCK_SIZE, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) set_cipher_config0(&desc[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) set_aes_not_hash_mode(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /* process assoc data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (req_ctx->assoclen > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) cc_set_assoc_desc(req, DIN_HASH, desc, &idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) set_din_type(&desc[idx], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) sg_dma_address(&req_ctx->ccm_adata_sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) AES_BLOCK_SIZE + req_ctx->ccm_hdr_size, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) set_flow_mode(&desc[idx], DIN_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /* process the cipher */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (req_ctx->cryptlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) cc_proc_cipher_desc(req, cipher_flow_mode, desc, &idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /* Read temporal MAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) set_cipher_mode(&desc[idx], DRV_CIPHER_CBC_MAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) set_dout_dlli(&desc[idx], req_ctx->mac_buf_dma_addr, ctx->authsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) NS_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) set_cipher_config0(&desc[idx], HASH_DIGEST_RESULT_LITTLE_ENDIAN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) set_flow_mode(&desc[idx], S_HASH_to_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) set_aes_not_hash_mode(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /* load AES-CTR state (for last MAC calculation)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) set_cipher_mode(&desc[idx], DRV_CIPHER_CTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) set_din_type(&desc[idx], DMA_DLLI, req_ctx->ccm_iv0_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) AES_BLOCK_SIZE, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) set_key_size_aes(&desc[idx], ctx->enc_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) set_setup_mode(&desc[idx], SETUP_LOAD_STATE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) set_flow_mode(&desc[idx], S_DIN_to_AES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) set_din_no_dma(&desc[idx], 0, 0xfffff0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) set_dout_no_dma(&desc[idx], 0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /* encrypt the "T" value and store MAC in mac_state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) set_din_type(&desc[idx], DMA_DLLI, req_ctx->mac_buf_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) ctx->authsize, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) set_dout_dlli(&desc[idx], mac_result, ctx->authsize, NS_BIT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) set_queue_last_ind(ctx->drvdata, &desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) set_flow_mode(&desc[idx], DIN_AES_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) *seq_size = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) static int config_ccm_adata(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct aead_req_ctx *req_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) //unsigned int size_of_a = 0, rem_a_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) unsigned int lp = req->iv[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* Note: The code assume that req->iv[0] already contains the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * of L' of RFC3610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) unsigned int l = lp + 1; /* This is L' of RFC 3610. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) unsigned int m = ctx->authsize; /* This is M' of RFC 3610. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) u8 *b0 = req_ctx->ccm_config + CCM_B0_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) u8 *a0 = req_ctx->ccm_config + CCM_A0_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) u8 *ctr_count_0 = req_ctx->ccm_config + CCM_CTR_COUNT_0_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) unsigned int cryptlen = (req_ctx->gen_ctx.op_type ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) DRV_CRYPTO_DIRECTION_ENCRYPT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) req->cryptlen :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) (req->cryptlen - ctx->authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) memset(req_ctx->mac_buf, 0, AES_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) memset(req_ctx->ccm_config, 0, AES_BLOCK_SIZE * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) /* taken from crypto/ccm.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) /* 2 <= L <= 8, so 1 <= L' <= 7. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (l < 2 || l > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) dev_dbg(dev, "illegal iv value %X\n", req->iv[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) memcpy(b0, req->iv, AES_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* format control info per RFC 3610 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * NIST Special Publication 800-38C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) *b0 |= (8 * ((m - 2) / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (req_ctx->assoclen > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) *b0 |= 64; /* Enable bit 6 if Adata exists. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) rc = set_msg_len(b0 + 16 - l, cryptlen, l); /* Write L'. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) dev_err(dev, "message len overflow detected");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /* END of "taken from crypto/ccm.c" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) /* l(a) - size of associated data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) req_ctx->ccm_hdr_size = format_ccm_a0(a0, req_ctx->assoclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) memset(req->iv + 15 - req->iv[0], 0, req->iv[0] + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) req->iv[15] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) memcpy(ctr_count_0, req->iv, AES_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) ctr_count_0[15] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) static void cc_proc_rfc4309_ccm(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /* L' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) memset(areq_ctx->ctr_iv, 0, AES_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) /* For RFC 4309, always use 4 bytes for message length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) * (at most 2^32-1 bytes).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) areq_ctx->ctr_iv[0] = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) /* In RFC 4309 there is an 11-bytes nonce+IV part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) * that we build here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) memcpy(areq_ctx->ctr_iv + CCM_BLOCK_NONCE_OFFSET, ctx->ctr_nonce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) CCM_BLOCK_NONCE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) memcpy(areq_ctx->ctr_iv + CCM_BLOCK_IV_OFFSET, req->iv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) CCM_BLOCK_IV_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) req->iv = areq_ctx->ctr_iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) static void cc_set_ghash_desc(struct aead_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) struct cc_hw_desc desc[], unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) struct aead_req_ctx *req_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) unsigned int idx = *seq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) /* load key to AES*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) set_cipher_mode(&desc[idx], DRV_CIPHER_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) set_din_type(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) ctx->enc_keylen, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) set_key_size_aes(&desc[idx], ctx->enc_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) set_flow_mode(&desc[idx], S_DIN_to_AES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) /* process one zero block to generate hkey */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) set_din_const(&desc[idx], 0x0, AES_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) set_dout_dlli(&desc[idx], req_ctx->hkey_dma_addr, AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) NS_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) set_flow_mode(&desc[idx], DIN_AES_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) /* Memory Barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) set_din_no_dma(&desc[idx], 0, 0xfffff0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) set_dout_no_dma(&desc[idx], 0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) /* Load GHASH subkey */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) set_din_type(&desc[idx], DMA_DLLI, req_ctx->hkey_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) AES_BLOCK_SIZE, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) set_dout_no_dma(&desc[idx], 0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) set_aes_not_hash_mode(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) set_cipher_mode(&desc[idx], DRV_HASH_HW_GHASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* Configure Hash Engine to work with GHASH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) * Since it was not possible to extend HASH submodes to add GHASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) * The following command is necessary in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) * select GHASH (according to HW designers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) set_din_no_dma(&desc[idx], 0, 0xfffff0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) set_dout_no_dma(&desc[idx], 0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) set_aes_not_hash_mode(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) set_cipher_mode(&desc[idx], DRV_HASH_HW_GHASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) set_cipher_do(&desc[idx], 1); //1=AES_SK RKEK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) /* Load GHASH initial STATE (which is 0). (for any hash there is an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) * initial state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) set_din_const(&desc[idx], 0x0, AES_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) set_dout_no_dma(&desc[idx], 0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) set_flow_mode(&desc[idx], S_DIN_to_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) set_aes_not_hash_mode(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) set_cipher_mode(&desc[idx], DRV_HASH_HW_GHASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) set_cipher_config1(&desc[idx], HASH_PADDING_ENABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) set_setup_mode(&desc[idx], SETUP_LOAD_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) *seq_size = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) static void cc_set_gctr_desc(struct aead_request *req, struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) struct aead_req_ctx *req_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) unsigned int idx = *seq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) /* load key to AES*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) set_cipher_mode(&desc[idx], DRV_CIPHER_GCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) set_din_type(&desc[idx], DMA_DLLI, ctx->enckey_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) ctx->enc_keylen, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) set_key_size_aes(&desc[idx], ctx->enc_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) set_setup_mode(&desc[idx], SETUP_LOAD_KEY0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) set_flow_mode(&desc[idx], S_DIN_to_AES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (req_ctx->cryptlen && !req_ctx->plaintext_authenticate_only) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /* load AES/CTR initial CTR value inc by 2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) set_cipher_mode(&desc[idx], DRV_CIPHER_GCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) set_key_size_aes(&desc[idx], ctx->enc_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) set_din_type(&desc[idx], DMA_DLLI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) req_ctx->gcm_iv_inc2_dma_addr, AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) set_setup_mode(&desc[idx], SETUP_LOAD_STATE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) set_flow_mode(&desc[idx], S_DIN_to_AES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) *seq_size = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static void cc_proc_gcm_result(struct aead_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) struct aead_req_ctx *req_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) dma_addr_t mac_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) unsigned int idx = *seq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (req_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) mac_result = req_ctx->mac_buf_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) } else { /* Encrypt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) mac_result = req_ctx->icv_dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) /* process(ghash) gcm_block_len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) set_din_type(&desc[idx], DMA_DLLI, req_ctx->gcm_block_len_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) AES_BLOCK_SIZE, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) set_flow_mode(&desc[idx], DIN_HASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /* Store GHASH state after GHASH(Associated Data + Cipher +LenBlock) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) set_cipher_mode(&desc[idx], DRV_HASH_HW_GHASH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) set_din_no_dma(&desc[idx], 0, 0xfffff0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) set_dout_dlli(&desc[idx], req_ctx->mac_buf_dma_addr, AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) NS_BIT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) set_setup_mode(&desc[idx], SETUP_WRITE_STATE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) set_flow_mode(&desc[idx], S_HASH_to_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) set_aes_not_hash_mode(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) /* load AES/CTR initial CTR value inc by 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) set_cipher_mode(&desc[idx], DRV_CIPHER_GCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) set_key_size_aes(&desc[idx], ctx->enc_keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) set_din_type(&desc[idx], DMA_DLLI, req_ctx->gcm_iv_inc1_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) AES_BLOCK_SIZE, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) set_cipher_config0(&desc[idx], DRV_CRYPTO_DIRECTION_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) set_setup_mode(&desc[idx], SETUP_LOAD_STATE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) set_flow_mode(&desc[idx], S_DIN_to_AES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /* Memory Barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) set_din_no_dma(&desc[idx], 0, 0xfffff0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) set_dout_no_dma(&desc[idx], 0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) /* process GCTR on stored GHASH and store MAC in mac_state*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) hw_desc_init(&desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) set_cipher_mode(&desc[idx], DRV_CIPHER_GCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) set_din_type(&desc[idx], DMA_DLLI, req_ctx->mac_buf_dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) AES_BLOCK_SIZE, NS_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) set_dout_dlli(&desc[idx], mac_result, ctx->authsize, NS_BIT, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) set_queue_last_ind(ctx->drvdata, &desc[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) set_flow_mode(&desc[idx], DIN_AES_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) *seq_size = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static int cc_gcm(struct aead_request *req, struct cc_hw_desc desc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) unsigned int *seq_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) struct aead_req_ctx *req_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) unsigned int cipher_flow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) //in RFC4543 no data to encrypt. just copy data from src to dest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) if (req_ctx->plaintext_authenticate_only) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) cc_proc_cipher_desc(req, BYPASS, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) cc_set_ghash_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) /* process(ghash) assoc data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) cc_set_assoc_desc(req, DIN_HASH, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) cc_set_gctr_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) cc_proc_gcm_result(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (req_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) cipher_flow_mode = AES_and_HASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) } else { /* Encrypt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) cipher_flow_mode = AES_to_HASH_and_DOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) // for gcm and rfc4106.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) cc_set_ghash_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) /* process(ghash) assoc data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) if (req_ctx->assoclen > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) cc_set_assoc_desc(req, DIN_HASH, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) cc_set_gctr_desc(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) /* process(gctr+ghash) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (req_ctx->cryptlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) cc_proc_cipher_desc(req, cipher_flow_mode, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) cc_proc_gcm_result(req, desc, seq_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) static int config_gcm_context(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) struct aead_req_ctx *req_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) unsigned int cryptlen = (req_ctx->gen_ctx.op_type ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) DRV_CRYPTO_DIRECTION_ENCRYPT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) req->cryptlen :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) (req->cryptlen - ctx->authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) __be32 counter = cpu_to_be32(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) dev_dbg(dev, "%s() cryptlen = %d, req_ctx->assoclen = %d ctx->authsize = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) __func__, cryptlen, req_ctx->assoclen, ctx->authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) memset(req_ctx->hkey, 0, AES_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) memset(req_ctx->mac_buf, 0, AES_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) memcpy(req->iv + 12, &counter, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) memcpy(req_ctx->gcm_iv_inc2, req->iv, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) counter = cpu_to_be32(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) memcpy(req->iv + 12, &counter, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) memcpy(req_ctx->gcm_iv_inc1, req->iv, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (!req_ctx->plaintext_authenticate_only) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) __be64 temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) temp64 = cpu_to_be64(req_ctx->assoclen * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) memcpy(&req_ctx->gcm_len_block.len_a, &temp64, sizeof(temp64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) temp64 = cpu_to_be64(cryptlen * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) memcpy(&req_ctx->gcm_len_block.len_c, &temp64, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) /* rfc4543=> all data(AAD,IV,Plain) are considered additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) * data that is nothing is encrypted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) __be64 temp64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) temp64 = cpu_to_be64((req_ctx->assoclen + cryptlen) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) memcpy(&req_ctx->gcm_len_block.len_a, &temp64, sizeof(temp64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) temp64 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) memcpy(&req_ctx->gcm_len_block.len_c, &temp64, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) static void cc_proc_rfc4_gcm(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) memcpy(areq_ctx->ctr_iv + GCM_BLOCK_RFC4_NONCE_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) ctx->ctr_nonce, GCM_BLOCK_RFC4_NONCE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) memcpy(areq_ctx->ctr_iv + GCM_BLOCK_RFC4_IV_OFFSET, req->iv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) GCM_BLOCK_RFC4_IV_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) req->iv = areq_ctx->ctr_iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) static int cc_proc_aead(struct aead_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) enum drv_crypto_direction direct)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) int seq_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) struct cc_hw_desc desc[MAX_AEAD_PROCESS_SEQ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) struct crypto_aead *tfm = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) struct cc_crypto_req cc_req = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) dev_dbg(dev, "%s context=%p req=%p iv=%p src=%p src_ofs=%d dst=%p dst_ofs=%d cryptolen=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) ((direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? "Enc" : "Dec"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) ctx, req, req->iv, sg_virt(req->src), req->src->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) sg_virt(req->dst), req->dst->offset, req->cryptlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) /* STAT_PHASE_0: Init and sanity checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) /* Check data length according to mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) if (validate_data_size(ctx, direct, req)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) dev_err(dev, "Unsupported crypt/assoc len %d/%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) req->cryptlen, areq_ctx->assoclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) /* Setup request structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) cc_req.user_cb = cc_aead_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) cc_req.user_arg = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) /* Setup request context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) areq_ctx->gen_ctx.op_type = direct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) areq_ctx->req_authsize = ctx->authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) areq_ctx->cipher_mode = ctx->cipher_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) /* STAT_PHASE_1: Map buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (ctx->cipher_mode == DRV_CIPHER_CTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) /* Build CTR IV - Copy nonce from last 4 bytes in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) * CTR key to first 4 bytes in CTR IV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) memcpy(areq_ctx->ctr_iv, ctx->ctr_nonce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) CTR_RFC3686_NONCE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) memcpy(areq_ctx->ctr_iv + CTR_RFC3686_NONCE_SIZE, req->iv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) CTR_RFC3686_IV_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) /* Initialize counter portion of counter block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) *(__be32 *)(areq_ctx->ctr_iv + CTR_RFC3686_NONCE_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) CTR_RFC3686_IV_SIZE) = cpu_to_be32(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) /* Replace with counter iv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) req->iv = areq_ctx->ctr_iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) areq_ctx->hw_iv_size = CTR_RFC3686_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) } else if ((ctx->cipher_mode == DRV_CIPHER_CCM) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) (ctx->cipher_mode == DRV_CIPHER_GCTR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) areq_ctx->hw_iv_size = AES_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) if (areq_ctx->ctr_iv != req->iv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) memcpy(areq_ctx->ctr_iv, req->iv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) crypto_aead_ivsize(tfm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) req->iv = areq_ctx->ctr_iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) areq_ctx->hw_iv_size = crypto_aead_ivsize(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (ctx->cipher_mode == DRV_CIPHER_CCM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) rc = config_ccm_adata(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) dev_dbg(dev, "config_ccm_adata() returned with a failure %d!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) areq_ctx->ccm_hdr_size = ccm_header_size_null;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) if (ctx->cipher_mode == DRV_CIPHER_GCTR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) rc = config_gcm_context(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) dev_dbg(dev, "config_gcm_context() returned with a failure %d!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) rc = cc_map_aead_request(ctx->drvdata, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) dev_err(dev, "map_request() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) /* STAT_PHASE_2: Create sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) /* Load MLLI tables to SRAM if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) cc_mlli_to_sram(req, desc, &seq_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) switch (ctx->auth_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) case DRV_HASH_SHA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) case DRV_HASH_SHA256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) cc_hmac_authenc(req, desc, &seq_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) case DRV_HASH_XCBC_MAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) cc_xcbc_authenc(req, desc, &seq_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) case DRV_HASH_NULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (ctx->cipher_mode == DRV_CIPHER_CCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) cc_ccm(req, desc, &seq_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) if (ctx->cipher_mode == DRV_CIPHER_GCTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) cc_gcm(req, desc, &seq_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) dev_err(dev, "Unsupported authenc (%d)\n", ctx->auth_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) cc_unmap_aead_request(dev, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) rc = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) /* STAT_PHASE_3: Lock HW and push sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) rc = cc_send_request(ctx->drvdata, &cc_req, desc, seq_len, &req->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) if (rc != -EINPROGRESS && rc != -EBUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) dev_err(dev, "send_request() failed (rc=%d)\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) cc_unmap_aead_request(dev, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) static int cc_aead_encrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) memset(areq_ctx, 0, sizeof(*areq_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) /* No generated IV required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) areq_ctx->backup_iv = req->iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) areq_ctx->assoclen = req->assoclen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) rc = cc_proc_aead(req, DRV_CRYPTO_DIRECTION_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) if (rc != -EINPROGRESS && rc != -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) req->iv = areq_ctx->backup_iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) static int cc_rfc4309_ccm_encrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) /* Very similar to cc_aead_encrypt() above. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) rc = crypto_ipsec_check_assoclen(req->assoclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) memset(areq_ctx, 0, sizeof(*areq_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) /* No generated IV required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) areq_ctx->backup_iv = req->iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) areq_ctx->assoclen = req->assoclen - CCM_BLOCK_IV_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) cc_proc_rfc4309_ccm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) rc = cc_proc_aead(req, DRV_CRYPTO_DIRECTION_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) if (rc != -EINPROGRESS && rc != -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) req->iv = areq_ctx->backup_iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) static int cc_aead_decrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) memset(areq_ctx, 0, sizeof(*areq_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) /* No generated IV required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) areq_ctx->backup_iv = req->iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) areq_ctx->assoclen = req->assoclen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) rc = cc_proc_aead(req, DRV_CRYPTO_DIRECTION_DECRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (rc != -EINPROGRESS && rc != -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) req->iv = areq_ctx->backup_iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) static int cc_rfc4309_ccm_decrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) rc = crypto_ipsec_check_assoclen(req->assoclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) memset(areq_ctx, 0, sizeof(*areq_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) /* No generated IV required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) areq_ctx->backup_iv = req->iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) areq_ctx->assoclen = req->assoclen - CCM_BLOCK_IV_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) cc_proc_rfc4309_ccm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) rc = cc_proc_aead(req, DRV_CRYPTO_DIRECTION_DECRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) if (rc != -EINPROGRESS && rc != -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) req->iv = areq_ctx->backup_iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) static int cc_rfc4106_gcm_setkey(struct crypto_aead *tfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) dev_dbg(dev, "%s() keylen %d, key %p\n", __func__, keylen, key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) if (keylen < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) keylen -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) memcpy(ctx->ctr_nonce, key + keylen, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) return cc_aead_setkey(tfm, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static int cc_rfc4543_gcm_setkey(struct crypto_aead *tfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) dev_dbg(dev, "%s() keylen %d, key %p\n", __func__, keylen, key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) if (keylen < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) keylen -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) memcpy(ctx->ctr_nonce, key + keylen, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) return cc_aead_setkey(tfm, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) static int cc_gcm_setauthsize(struct crypto_aead *authenc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) switch (authsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) case 13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) case 14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) case 15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) return cc_aead_setauthsize(authenc, authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) static int cc_rfc4106_gcm_setauthsize(struct crypto_aead *authenc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) struct cc_aead_ctx *ctx = crypto_aead_ctx(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) dev_dbg(dev, "authsize %d\n", authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) switch (authsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) return cc_aead_setauthsize(authenc, authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) static int cc_rfc4543_gcm_setauthsize(struct crypto_aead *authenc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) struct cc_aead_ctx *ctx = crypto_aead_ctx(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) struct device *dev = drvdata_to_dev(ctx->drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) dev_dbg(dev, "authsize %d\n", authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) if (authsize != 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) return cc_aead_setauthsize(authenc, authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) static int cc_rfc4106_gcm_encrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) rc = crypto_ipsec_check_assoclen(req->assoclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) memset(areq_ctx, 0, sizeof(*areq_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) /* No generated IV required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) areq_ctx->backup_iv = req->iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) areq_ctx->assoclen = req->assoclen - GCM_BLOCK_RFC4_IV_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) cc_proc_rfc4_gcm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) rc = cc_proc_aead(req, DRV_CRYPTO_DIRECTION_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) if (rc != -EINPROGRESS && rc != -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) req->iv = areq_ctx->backup_iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) static int cc_rfc4543_gcm_encrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) rc = crypto_ipsec_check_assoclen(req->assoclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) memset(areq_ctx, 0, sizeof(*areq_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) //plaintext is not encryped with rfc4543
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) areq_ctx->plaintext_authenticate_only = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) /* No generated IV required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) areq_ctx->backup_iv = req->iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) areq_ctx->assoclen = req->assoclen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) cc_proc_rfc4_gcm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) rc = cc_proc_aead(req, DRV_CRYPTO_DIRECTION_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) if (rc != -EINPROGRESS && rc != -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) req->iv = areq_ctx->backup_iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) static int cc_rfc4106_gcm_decrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) rc = crypto_ipsec_check_assoclen(req->assoclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) memset(areq_ctx, 0, sizeof(*areq_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) /* No generated IV required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) areq_ctx->backup_iv = req->iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) areq_ctx->assoclen = req->assoclen - GCM_BLOCK_RFC4_IV_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) cc_proc_rfc4_gcm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) rc = cc_proc_aead(req, DRV_CRYPTO_DIRECTION_DECRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) if (rc != -EINPROGRESS && rc != -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) req->iv = areq_ctx->backup_iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) static int cc_rfc4543_gcm_decrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) struct aead_req_ctx *areq_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) rc = crypto_ipsec_check_assoclen(req->assoclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) memset(areq_ctx, 0, sizeof(*areq_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) //plaintext is not decryped with rfc4543
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) areq_ctx->plaintext_authenticate_only = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) /* No generated IV required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) areq_ctx->backup_iv = req->iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) areq_ctx->assoclen = req->assoclen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) cc_proc_rfc4_gcm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) rc = cc_proc_aead(req, DRV_CRYPTO_DIRECTION_DECRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) if (rc != -EINPROGRESS && rc != -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) req->iv = areq_ctx->backup_iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) /* aead alg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) static struct cc_alg_template aead_algs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .name = "authenc(hmac(sha1),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .driver_name = "authenc-hmac-sha1-cbc-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .template_aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .setkey = cc_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .setauthsize = cc_aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .encrypt = cc_aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .decrypt = cc_aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .init = cc_aead_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .exit = cc_aead_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .cipher_mode = DRV_CIPHER_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .auth_mode = DRV_HASH_SHA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .name = "authenc(hmac(sha1),cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .driver_name = "authenc-hmac-sha1-cbc-des3-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .template_aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .setkey = cc_des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .setauthsize = cc_aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .encrypt = cc_aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) .decrypt = cc_aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .init = cc_aead_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) .exit = cc_aead_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .cipher_mode = DRV_CIPHER_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .flow_mode = S_DIN_to_DES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .auth_mode = DRV_HASH_SHA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .name = "authenc(hmac(sha256),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .driver_name = "authenc-hmac-sha256-cbc-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .template_aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .setkey = cc_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .setauthsize = cc_aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .encrypt = cc_aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .decrypt = cc_aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .init = cc_aead_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .exit = cc_aead_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .cipher_mode = DRV_CIPHER_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .auth_mode = DRV_HASH_SHA256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .name = "authenc(hmac(sha256),cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .driver_name = "authenc-hmac-sha256-cbc-des3-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .template_aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .setkey = cc_des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .setauthsize = cc_aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .encrypt = cc_aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .decrypt = cc_aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .init = cc_aead_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .exit = cc_aead_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) .cipher_mode = DRV_CIPHER_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .flow_mode = S_DIN_to_DES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) .auth_mode = DRV_HASH_SHA256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .name = "authenc(xcbc(aes),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .driver_name = "authenc-xcbc-aes-cbc-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .template_aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .setkey = cc_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .setauthsize = cc_aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .encrypt = cc_aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .decrypt = cc_aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .init = cc_aead_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .exit = cc_aead_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .cipher_mode = DRV_CIPHER_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .auth_mode = DRV_HASH_XCBC_MAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .name = "authenc(hmac(sha1),rfc3686(ctr(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .driver_name = "authenc-hmac-sha1-rfc3686-ctr-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .template_aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .setkey = cc_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .setauthsize = cc_aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .encrypt = cc_aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .decrypt = cc_aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .init = cc_aead_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .exit = cc_aead_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .cipher_mode = DRV_CIPHER_CTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .auth_mode = DRV_HASH_SHA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) .name = "authenc(hmac(sha256),rfc3686(ctr(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .driver_name = "authenc-hmac-sha256-rfc3686-ctr-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .template_aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .setkey = cc_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .setauthsize = cc_aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) .encrypt = cc_aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .decrypt = cc_aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .init = cc_aead_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .exit = cc_aead_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .cipher_mode = DRV_CIPHER_CTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .auth_mode = DRV_HASH_SHA256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .name = "authenc(xcbc(aes),rfc3686(ctr(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .driver_name = "authenc-xcbc-aes-rfc3686-ctr-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) .blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .template_aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) .setkey = cc_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .setauthsize = cc_aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .encrypt = cc_aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .decrypt = cc_aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) .init = cc_aead_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .exit = cc_aead_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .cipher_mode = DRV_CIPHER_CTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .auth_mode = DRV_HASH_XCBC_MAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .name = "ccm(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .driver_name = "ccm-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .template_aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .setkey = cc_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .setauthsize = cc_ccm_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) .encrypt = cc_aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .decrypt = cc_aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .init = cc_aead_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .exit = cc_aead_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .cipher_mode = DRV_CIPHER_CCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .auth_mode = DRV_HASH_NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .name = "rfc4309(ccm(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .driver_name = "rfc4309-ccm-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) .template_aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) .setkey = cc_rfc4309_ccm_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) .setauthsize = cc_rfc4309_ccm_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) .encrypt = cc_rfc4309_ccm_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) .decrypt = cc_rfc4309_ccm_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) .init = cc_aead_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .exit = cc_aead_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .ivsize = CCM_BLOCK_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .cipher_mode = DRV_CIPHER_CCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .auth_mode = DRV_HASH_NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .name = "gcm(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .driver_name = "gcm-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) .blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) .template_aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) .setkey = cc_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .setauthsize = cc_gcm_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .encrypt = cc_aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .decrypt = cc_aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .init = cc_aead_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .exit = cc_aead_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .ivsize = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .cipher_mode = DRV_CIPHER_GCTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .auth_mode = DRV_HASH_NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .name = "rfc4106(gcm(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .driver_name = "rfc4106-gcm-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .template_aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .setkey = cc_rfc4106_gcm_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .setauthsize = cc_rfc4106_gcm_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) .encrypt = cc_rfc4106_gcm_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .decrypt = cc_rfc4106_gcm_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .init = cc_aead_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .exit = cc_aead_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) .ivsize = GCM_BLOCK_RFC4_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) .cipher_mode = DRV_CIPHER_GCTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .auth_mode = DRV_HASH_NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .name = "rfc4543(gcm(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .driver_name = "rfc4543-gcm-aes-ccree",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .template_aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) .setkey = cc_rfc4543_gcm_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) .setauthsize = cc_rfc4543_gcm_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) .encrypt = cc_rfc4543_gcm_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) .decrypt = cc_rfc4543_gcm_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .init = cc_aead_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .exit = cc_aead_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .ivsize = GCM_BLOCK_RFC4_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .cipher_mode = DRV_CIPHER_GCTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .flow_mode = S_DIN_to_AES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .auth_mode = DRV_HASH_NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .min_hw_rev = CC_HW_REV_630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .std_body = CC_STD_NIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) static struct cc_crypto_alg *cc_create_aead_alg(struct cc_alg_template *tmpl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) struct cc_crypto_alg *t_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) struct aead_alg *alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) t_alg = devm_kzalloc(dev, sizeof(*t_alg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) if (!t_alg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) alg = &tmpl->template_aead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) tmpl->driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) alg->base.cra_module = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) alg->base.cra_priority = CC_CRA_PRIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) alg->base.cra_ctxsize = sizeof(struct cc_aead_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) alg->base.cra_blocksize = tmpl->blocksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) alg->init = cc_aead_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) alg->exit = cc_aead_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) t_alg->aead_alg = *alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) t_alg->cipher_mode = tmpl->cipher_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) t_alg->flow_mode = tmpl->flow_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) t_alg->auth_mode = tmpl->auth_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) return t_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) int cc_aead_free(struct cc_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) struct cc_crypto_alg *t_alg, *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) struct cc_aead_handle *aead_handle = drvdata->aead_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) /* Remove registered algs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) list_for_each_entry_safe(t_alg, n, &aead_handle->aead_list, entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) crypto_unregister_aead(&t_alg->aead_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) list_del(&t_alg->entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) int cc_aead_alloc(struct cc_drvdata *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) struct cc_aead_handle *aead_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) struct cc_crypto_alg *t_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) int rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) int alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) struct device *dev = drvdata_to_dev(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) aead_handle = devm_kmalloc(dev, sizeof(*aead_handle), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) if (!aead_handle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) INIT_LIST_HEAD(&aead_handle->aead_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) drvdata->aead_handle = aead_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) aead_handle->sram_workspace_addr = cc_sram_alloc(drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) MAX_HMAC_DIGEST_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) if (aead_handle->sram_workspace_addr == NULL_SRAM_ADDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) /* Linux crypto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) for (alg = 0; alg < ARRAY_SIZE(aead_algs); alg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) if ((aead_algs[alg].min_hw_rev > drvdata->hw_rev) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) !(drvdata->std_bodies & aead_algs[alg].std_body))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) t_alg = cc_create_aead_alg(&aead_algs[alg], dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) if (IS_ERR(t_alg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) rc = PTR_ERR(t_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) dev_err(dev, "%s alg allocation failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) aead_algs[alg].driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) t_alg->drvdata = drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) rc = crypto_register_aead(&t_alg->aead_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) dev_err(dev, "%s alg registration failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) t_alg->aead_alg.base.cra_driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) list_add_tail(&t_alg->entry, &aead_handle->aead_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) dev_dbg(dev, "Registered %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) t_alg->aead_alg.base.cra_driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) cc_aead_free(drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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