^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AMD Secure Processor device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013,2019 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Tom Lendacky <thomas.lendacky@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Gary R Hook <gary.hook@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/ccp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "ccp-dev.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "psp-dev.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MSIX_VECTORS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct sp_pci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int msix_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct msix_entry msix_entry[MSIX_VECTORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct sp_device *sp_dev_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int sp_get_msix_irqs(struct sp_device *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct sp_pci *sp_pci = sp->dev_specific;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct device *dev = sp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int v, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) for (v = 0; v < ARRAY_SIZE(sp_pci->msix_entry); v++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) sp_pci->msix_entry[v].entry = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ret = pci_enable_msix_range(pdev, sp_pci->msix_entry, 1, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) sp_pci->msix_count = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) sp->use_tasklet = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) sp->psp_irq = sp_pci->msix_entry[0].vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) sp->ccp_irq = (sp_pci->msix_count > 1) ? sp_pci->msix_entry[1].vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) : sp_pci->msix_entry[0].vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int sp_get_msi_irq(struct sp_device *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct device *dev = sp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ret = pci_enable_msi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) sp->ccp_irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) sp->psp_irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int sp_get_irqs(struct sp_device *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct device *dev = sp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = sp_get_msix_irqs(sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Couldn't get MSI-X vectors, try MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dev_notice(dev, "could not enable MSI-X (%d), trying MSI\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ret = sp_get_msi_irq(sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Couldn't get MSI interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dev_notice(dev, "could not enable MSI (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void sp_free_irqs(struct sp_device *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct sp_pci *sp_pci = sp->dev_specific;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct device *dev = sp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (sp_pci->msix_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pci_disable_msix(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) else if (sp->psp_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pci_disable_msi(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) sp->ccp_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) sp->psp_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static bool sp_pci_is_master(struct sp_device *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct device *dev_cur, *dev_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct pci_dev *pdev_cur, *pdev_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dev_new = sp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_cur = sp_dev_master->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pdev_new = to_pci_dev(dev_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) pdev_cur = to_pci_dev(dev_cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (pdev_new->bus->number < pdev_cur->bus->number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (PCI_SLOT(pdev_new->devfn) < PCI_SLOT(pdev_cur->devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (PCI_FUNC(pdev_new->devfn) < PCI_FUNC(pdev_cur->devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void psp_set_master(struct sp_device *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (!sp_dev_master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) sp_dev_master = sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (sp_pci_is_master(sp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) sp_dev_master = sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct sp_device *psp_get_master(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return sp_dev_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void psp_clear_master(struct sp_device *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (sp == sp_dev_master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) sp_dev_master = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_dbg(sp->dev, "Cleared sp_dev_master\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int sp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct sp_device *sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct sp_pci *sp_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) void __iomem * const *iomap_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int bar_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) sp = sp_alloc_struct(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (!sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) goto e_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) sp_pci = devm_kzalloc(dev, sizeof(*sp_pci), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!sp_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) goto e_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) sp->dev_specific = sp_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) sp->dev_vdata = (struct sp_dev_vdata *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!sp->dev_vdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_err(dev, "missing driver data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) goto e_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev_err(dev, "pcim_enable_device failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) goto e_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) bar_mask = pci_select_bars(pdev, IORESOURCE_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret = pcim_iomap_regions(pdev, bar_mask, "ccp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_err(dev, "pcim_iomap_regions failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) goto e_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) iomap_table = pcim_iomap_table(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (!iomap_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_err(dev, "pcim_iomap_table failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) goto e_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) sp->io_map = iomap_table[sp->dev_vdata->bar];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!sp->io_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_err(dev, "ioremap failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) goto e_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = sp_get_irqs(sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) goto e_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) sp->set_psp_master_device = psp_set_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) sp->get_psp_master_device = psp_get_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) sp->clear_psp_master_device = psp_clear_master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) goto free_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_set_drvdata(dev, sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = sp_init(sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto free_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) free_irqs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) sp_free_irqs(sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) e_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_notice(dev, "initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void sp_pci_shutdown(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct sp_device *sp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) sp_destroy(sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static void sp_pci_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct sp_device *sp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (!sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) sp_destroy(sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) sp_free_irqs(sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int __maybe_unused sp_pci_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct sp_device *sp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return sp_suspend(sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int __maybe_unused sp_pci_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct sp_device *sp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return sp_resume(sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #ifdef CONFIG_CRYPTO_DEV_SP_PSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const struct sev_vdata sevv1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .cmdresp_reg = 0x10580,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .cmdbuff_addr_lo_reg = 0x105e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .cmdbuff_addr_hi_reg = 0x105e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const struct sev_vdata sevv2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .cmdresp_reg = 0x10980,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .cmdbuff_addr_lo_reg = 0x109e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .cmdbuff_addr_hi_reg = 0x109e4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const struct tee_vdata teev1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .cmdresp_reg = 0x10544,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .cmdbuff_addr_lo_reg = 0x10548,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .cmdbuff_addr_hi_reg = 0x1054c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .ring_wptr_reg = 0x10550,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .ring_rptr_reg = 0x10554,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const struct psp_vdata pspv1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .sev = &sevv1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .feature_reg = 0x105fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .inten_reg = 0x10610,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .intsts_reg = 0x10614,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const struct psp_vdata pspv2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .sev = &sevv2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .feature_reg = 0x109fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .inten_reg = 0x10690,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .intsts_reg = 0x10694,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const struct psp_vdata pspv3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .tee = &teev1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .feature_reg = 0x109fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .inten_reg = 0x10690,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .intsts_reg = 0x10694,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const struct sp_dev_vdata dev_vdata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .bar = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #ifdef CONFIG_CRYPTO_DEV_SP_CCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .ccp_vdata = &ccpv3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .bar = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #ifdef CONFIG_CRYPTO_DEV_SP_CCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .ccp_vdata = &ccpv5a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #ifdef CONFIG_CRYPTO_DEV_SP_PSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .psp_vdata = &pspv1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .bar = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #ifdef CONFIG_CRYPTO_DEV_SP_CCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .ccp_vdata = &ccpv5b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .bar = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #ifdef CONFIG_CRYPTO_DEV_SP_CCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .ccp_vdata = &ccpv5a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #ifdef CONFIG_CRYPTO_DEV_SP_PSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .psp_vdata = &pspv2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { /* 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .bar = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #ifdef CONFIG_CRYPTO_DEV_SP_CCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .ccp_vdata = &ccpv5a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #ifdef CONFIG_CRYPTO_DEV_SP_PSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .psp_vdata = &pspv3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct pci_device_id sp_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { PCI_VDEVICE(AMD, 0x1537), (kernel_ulong_t)&dev_vdata[0] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { PCI_VDEVICE(AMD, 0x1456), (kernel_ulong_t)&dev_vdata[1] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { PCI_VDEVICE(AMD, 0x1468), (kernel_ulong_t)&dev_vdata[2] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { PCI_VDEVICE(AMD, 0x1486), (kernel_ulong_t)&dev_vdata[3] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { PCI_VDEVICE(AMD, 0x15DF), (kernel_ulong_t)&dev_vdata[4] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Last entry must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MODULE_DEVICE_TABLE(pci, sp_pci_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static SIMPLE_DEV_PM_OPS(sp_pci_pm_ops, sp_pci_suspend, sp_pci_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct pci_driver sp_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .name = "ccp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .id_table = sp_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .probe = sp_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .remove = sp_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .shutdown = sp_pci_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .driver.pm = &sp_pci_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int sp_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return pci_register_driver(&sp_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) void sp_pci_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pci_unregister_driver(&sp_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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