^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AMD Secure Processor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017-2019 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Tom Lendacky <thomas.lendacky@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Gary R Hook <gary.hook@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Brijesh Singh <brijesh.singh@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __SP_DEV_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __SP_DEV_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SP_MAX_NAME_LEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CACHE_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CACHE_WB_NO_ALLOC 0xb7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Structure to hold CCP device data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct ccp_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct ccp_vdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) const unsigned int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) const unsigned int dma_chan_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void (*setup)(struct ccp_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) const struct ccp_actions *perform;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) const unsigned int rsamax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct sev_vdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const unsigned int cmdresp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) const unsigned int cmdbuff_addr_lo_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) const unsigned int cmdbuff_addr_hi_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct tee_vdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) const unsigned int cmdresp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) const unsigned int cmdbuff_addr_lo_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const unsigned int cmdbuff_addr_hi_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const unsigned int ring_wptr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const unsigned int ring_rptr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct psp_vdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) const struct sev_vdata *sev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const struct tee_vdata *tee;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) const unsigned int feature_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const unsigned int inten_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) const unsigned int intsts_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Structure to hold SP device data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct sp_dev_vdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) const unsigned int bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) const struct ccp_vdata *ccp_vdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) const struct psp_vdata *psp_vdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct sp_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct sp_dev_vdata *dev_vdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int ord;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) char name[SP_MAX_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Bus specific device information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void *dev_specific;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* I/O area used for device communication. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void __iomem *io_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* DMA caching attribute support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int axcache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* get and set master device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct sp_device*(*get_psp_master_device)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void (*set_psp_master_device)(struct sp_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void (*clear_psp_master_device)(struct sp_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) bool irq_registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) bool use_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int ccp_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) irq_handler_t ccp_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void *ccp_irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int psp_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) irq_handler_t psp_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void *psp_irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) void *ccp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void *psp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int sp_pci_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void sp_pci_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int sp_platform_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void sp_platform_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct sp_device *sp_alloc_struct(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int sp_init(struct sp_device *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void sp_destroy(struct sp_device *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct sp_device *sp_get_master(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int sp_suspend(struct sp_device *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int sp_resume(struct sp_device *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int sp_request_ccp_irq(struct sp_device *sp, irq_handler_t handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const char *name, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void sp_free_ccp_irq(struct sp_device *sp, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int sp_request_psp_irq(struct sp_device *sp, irq_handler_t handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const char *name, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void sp_free_psp_irq(struct sp_device *sp, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct sp_device *sp_get_psp_master_device(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #ifdef CONFIG_CRYPTO_DEV_SP_CCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int ccp_dev_init(struct sp_device *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void ccp_dev_destroy(struct sp_device *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int ccp_dev_suspend(struct sp_device *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int ccp_dev_resume(struct sp_device *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #else /* !CONFIG_CRYPTO_DEV_SP_CCP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline int ccp_dev_init(struct sp_device *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static inline void ccp_dev_destroy(struct sp_device *sp) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static inline int ccp_dev_suspend(struct sp_device *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static inline int ccp_dev_resume(struct sp_device *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif /* CONFIG_CRYPTO_DEV_SP_CCP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #ifdef CONFIG_CRYPTO_DEV_SP_PSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int psp_dev_init(struct sp_device *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) void psp_pci_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) void psp_dev_destroy(struct sp_device *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) void psp_pci_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #else /* !CONFIG_CRYPTO_DEV_SP_PSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static inline int psp_dev_init(struct sp_device *sp) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static inline void psp_pci_init(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static inline void psp_dev_destroy(struct sp_device *sp) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline void psp_pci_exit(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif /* CONFIG_CRYPTO_DEV_SP_PSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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