^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AMD Cryptographic Coprocessor (CCP) driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013,2017 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Tom Lendacky <thomas.lendacky@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Gary R Hook <gary.hook@amd.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __CCP_DEV_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __CCP_DEV_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/dma-direction.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "sp-dev.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MAX_CCP_NAME_LEN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MAX_DMAPOOL_NAME_LEN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MAX_HW_QUEUES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MAX_CMD_QLEN 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TRNG_RETRIES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CACHE_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CACHE_WB_NO_ALLOC 0xb7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /****** Register Mappings ******/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define Q_MASK_REG 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TRNG_OUT_REG 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IRQ_MASK_REG 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IRQ_STATUS_REG 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DEL_CMD_Q_JOB 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DEL_Q_ACTIVE 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DEL_Q_ID_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CMD_REQ0 0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CMD_REQ_INCR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CMD_Q_STATUS_BASE 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CMD_Q_INT_STATUS_BASE 0x214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CMD_Q_STATUS_INCR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CMD_Q_CACHE_BASE 0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CMD_Q_CACHE_INC 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CMD_Q_ERROR(__qs) ((__qs) & 0x0000003f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CMD_Q_DEPTH(__qs) (((__qs) >> 12) & 0x0000000f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* ------------------------ CCP Version 5 Specifics ------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CMD5_QUEUE_MASK_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CMD5_QUEUE_PRIO_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CMD5_REQID_CONFIG_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CMD5_CMD_TIMEOUT_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LSB_PUBLIC_MASK_LO_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LSB_PUBLIC_MASK_HI_OFFSET 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LSB_PRIVATE_MASK_LO_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LSB_PRIVATE_MASK_HI_OFFSET 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CMD5_PSP_CCP_VERSION 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CMD5_Q_CONTROL_BASE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CMD5_Q_TAIL_LO_BASE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CMD5_Q_HEAD_LO_BASE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CMD5_Q_INT_ENABLE_BASE 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CMD5_Q_INTERRUPT_STATUS_BASE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CMD5_Q_STATUS_BASE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CMD5_Q_INT_STATUS_BASE 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CMD5_Q_DMA_STATUS_BASE 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CMD5_Q_DMA_READ_STATUS_BASE 0x010C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CMD5_Q_DMA_WRITE_STATUS_BASE 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CMD5_Q_ABORT_BASE 0x0114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CMD5_Q_AX_CACHE_BASE 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CMD5_CONFIG_0_OFFSET 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CMD5_TRNG_CTL_OFFSET 0x6008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CMD5_AES_MASK_OFFSET 0x6010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CMD5_CLK_GATE_CTL_OFFSET 0x603C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Address offset between two virtual queue registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CMD5_Q_STATUS_INCR 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CMD5_Q_RUN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CMD5_Q_HALT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CMD5_Q_MEM_LOCATION 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CMD5_Q_SIZE 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CMD5_Q_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define COMMANDS_PER_QUEUE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define QUEUE_SIZE_VAL ((ffs(COMMANDS_PER_QUEUE) - 2) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) CMD5_Q_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define Q_DESC_SIZE sizeof(struct ccp5_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define Q_SIZE(n) (COMMANDS_PER_QUEUE*(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define INT_COMPLETION 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define INT_ERROR 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define INT_QUEUE_STOPPED 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define INT_EMPTY_QUEUE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SUPPORTED_INTERRUPTS (INT_COMPLETION | INT_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LSB_REGION_WIDTH 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MAX_LSB_CNT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define LSB_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define LSB_ITEM_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PLSB_MAP_SIZE (LSB_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SLSB_MAP_SIZE (MAX_LSB_CNT * LSB_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LSB_ENTRY_NUMBER(LSB_ADDR) (LSB_ADDR / LSB_ITEM_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* ------------------------ CCP Version 3 Specifics ------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define REQ0_WAIT_FOR_WRITE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define REQ0_INT_ON_COMPLETE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define REQ0_STOP_ON_COMPLETE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define REQ0_CMD_Q_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define REQ0_JOBID_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /****** REQ1 Related Values ******/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define REQ1_PROTECT_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define REQ1_ENGINE_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define REQ1_KEY_KSB_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define REQ1_EOM 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define REQ1_INIT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* AES Related Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define REQ1_AES_TYPE_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define REQ1_AES_MODE_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define REQ1_AES_ACTION_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define REQ1_AES_CFB_SIZE_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* XTS-AES Related Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define REQ1_XTS_AES_SIZE_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* SHA Related Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define REQ1_SHA_TYPE_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* RSA Related Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define REQ1_RSA_MOD_SIZE_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Pass-Through Related Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define REQ1_PT_BW_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define REQ1_PT_BS_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* ECC Related Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define REQ1_ECC_AFFINE_CONVERT 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define REQ1_ECC_FUNCTION_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /****** REQ4 Related Values ******/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define REQ4_KSB_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define REQ4_MEMTYPE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /****** REQ6 Related Values ******/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define REQ6_MEMTYPE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /****** Key Storage Block ******/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define KSB_START 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define KSB_END 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define KSB_COUNT (KSB_END - KSB_START + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CCP_SB_BITS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CCP_JOBID_MASK 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* ------------------------ General CCP Defines ------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CCP_DMA_DFLT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CCP_DMA_PRIV 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CCP_DMA_PUB 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CCP_DMAPOOL_MAX_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CCP_DMAPOOL_ALIGN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CCP_REVERSE_BUF_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CCP_AES_KEY_SB_COUNT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CCP_AES_CTX_SB_COUNT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CCP_XTS_AES_KEY_SB_COUNT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CCP5_XTS_AES_KEY_SB_COUNT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CCP_XTS_AES_CTX_SB_COUNT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CCP_DES3_KEY_SB_COUNT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CCP_DES3_CTX_SB_COUNT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CCP_SHA_SB_COUNT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CCP_RSA_MAX_WIDTH 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CCP5_RSA_MAX_WIDTH 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CCP_PASSTHRU_BLOCKSIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CCP_PASSTHRU_MASKSIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CCP_PASSTHRU_SB_COUNT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CCP_ECC_MODULUS_BYTES 48 /* 384-bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CCP_ECC_MAX_OPERANDS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CCP_ECC_MAX_OUTPUTS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CCP_ECC_SRC_BUF_SIZE 448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CCP_ECC_DST_BUF_SIZE 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CCP_ECC_OPERAND_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CCP_ECC_OUTPUT_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CCP_ECC_RESULT_OFFSET 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CCP_ECC_RESULT_SUCCESS 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CCP_SB_BYTES 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct ccp_op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct ccp_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct ccp_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct ccp_fns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct ccp_dma_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct ccp_cmd ccp_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct ccp_dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct ccp_device *ccp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct list_head pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct list_head active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct dma_async_tx_descriptor tx_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct ccp_dma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct ccp_device *ccp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct list_head created;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct list_head pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct list_head active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct list_head complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct tasklet_struct cleanup_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct dma_chan dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct ccp_cmd_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct ccp_device *ccp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Queue identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Queue dma pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct dma_pool *dma_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Queue base address (not neccessarily aligned)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct ccp5_desc *qbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Aligned queue start address (per requirement) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct mutex q_mutex ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned int qidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Version 5 has different requirements for queue memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned int qsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dma_addr_t qbase_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dma_addr_t qdma_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Per-queue reserved storage block(s) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 sb_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 sb_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Bitmap of LSBs that can be accessed by this queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DECLARE_BITMAP(lsbmask, MAX_LSB_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Private LSB that is assigned to this queue, or -1 if none.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Bitmap for my private LSB, unused otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) DECLARE_BITMAP(lsbmap, PLSB_MAP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Queue processing thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct task_struct *kthread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned int suspended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Number of free command slots available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int free_slots;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Interrupt masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 int_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 int_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Register addresses for queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) void __iomem *reg_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) void __iomem *reg_tail_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) void __iomem *reg_head_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) void __iomem *reg_int_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) void __iomem *reg_interrupt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) void __iomem *reg_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) void __iomem *reg_int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) void __iomem *reg_dma_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) void __iomem *reg_dma_read_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) void __iomem *reg_dma_write_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 qcontrol; /* Cached control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Status values from job */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 q_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 q_int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 cmd_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Interrupt wait queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) wait_queue_head_t int_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned int int_rcvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Per-queue Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) unsigned long total_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned long total_aes_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned long total_xts_aes_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned long total_3des_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned long total_sha_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned long total_rsa_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned long total_pt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned long total_ecc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct ccp_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct ccp_vdata *vdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned int ord;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) char name[MAX_CCP_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) char rngname[MAX_CCP_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct sp_device *sp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Bus specific device information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) void *dev_specific;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned int qim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) bool use_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct tasklet_struct irq_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* I/O area used for device communication. The register mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * starts at an offset into the mapped bar.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * The CMD_REQx registers and the Delete_Cmd_Queue_Job register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * need to be protected while a command queue thread is accessing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct mutex req_mutex ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) void __iomem *io_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Master lists that all cmds are queued on. Because there can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * more than one CCP command queue that can process a cmd a separate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * backlog list is neeeded so that the backlog completion call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * completes before the cmd is available for execution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) spinlock_t cmd_lock ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned int cmd_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct list_head cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct list_head backlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* The command queues. These represent the queues available on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * CCP that are available for processing cmds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct ccp_cmd_queue cmd_q[MAX_HW_QUEUES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned int cmd_q_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int max_q_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Support for the CCP True RNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct hwrng hwrng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned int hwrng_retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Support for the CCP DMA capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct dma_device dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct ccp_dma_chan *ccp_dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct kmem_cache *dma_cmd_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct kmem_cache *dma_desc_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* A counter used to generate job-ids for cmds submitted to the CCP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) atomic_t current_id ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* The v3 CCP uses key storage blocks (SB) to maintain context for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * certain operations. To prevent multiple cmds from using the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * SB range a command queue reserves an SB range for the duration of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * the cmd. Each queue, will however, reserve 2 SB blocks for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * operations that only require single SB entries (eg. AES context/iv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * and key) in order to avoid allocation contention. This will reserve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * at most 10 SB entries, leaving 40 SB entries available for dynamic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * allocation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * The v5 CCP Local Storage Block (LSB) is broken up into 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * memrory ranges, each of which can be enabled for access by one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * or more queues. Device initialization takes this into account,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * and attempts to assign one region for exclusive use by each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * available queue; the rest are then aggregated as "public" use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * If there are fewer regions than queues, all regions are shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * amongst all queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct mutex sb_mutex ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DECLARE_BITMAP(sb, KSB_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) wait_queue_head_t sb_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned int sb_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int sb_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 sb_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Bitmap of shared LSBs, if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) DECLARE_BITMAP(lsbmap, SLSB_MAP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Suspend support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned int suspending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) wait_queue_head_t suspend_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* DMA caching attribute support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) unsigned int axcache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Device Statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned long total_interrupts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* DebugFS info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct dentry *debugfs_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) enum ccp_memtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) CCP_MEMTYPE_SYSTEM = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) CCP_MEMTYPE_SB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) CCP_MEMTYPE_LOCAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) CCP_MEMTYPE__LAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define CCP_MEMTYPE_LSB CCP_MEMTYPE_KSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct ccp_dma_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dma_addr_t address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) enum dma_data_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) } __packed __aligned(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct ccp_dm_workarea {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct dma_pool *dma_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u8 *address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct ccp_dma_info dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct ccp_sg_workarea {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) unsigned int sg_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct scatterlist *dma_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct scatterlist *dma_sg_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct device *dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) unsigned int dma_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) enum dma_data_direction dma_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u64 bytes_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct ccp_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct ccp_sg_workarea sg_wa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct ccp_dm_workarea dm_wa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct ccp_mem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) enum ccp_memtype type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct ccp_dma_info dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u32 sb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct ccp_aes_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) enum ccp_aes_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) enum ccp_aes_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) enum ccp_aes_action action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct ccp_xts_aes_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) enum ccp_aes_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) enum ccp_aes_action action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) enum ccp_xts_aes_unit_size unit_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct ccp_des3_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) enum ccp_des3_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) enum ccp_des3_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) enum ccp_des3_action action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct ccp_sha_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) enum ccp_sha_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u64 msg_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct ccp_rsa_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u32 mod_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 input_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct ccp_passthru_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) enum ccp_passthru_bitwise bit_mod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) enum ccp_passthru_byteswap byte_swap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct ccp_ecc_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) enum ccp_ecc_function function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct ccp_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct ccp_cmd_queue *cmd_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 jobid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u32 ioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u32 soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u32 sb_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u32 sb_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u32 init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 eom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct ccp_mem src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct ccp_mem dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct ccp_mem exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct ccp_aes_op aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct ccp_xts_aes_op xts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct ccp_des3_op des3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct ccp_sha_op sha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct ccp_rsa_op rsa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct ccp_passthru_op passthru;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct ccp_ecc_op ecc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static inline u32 ccp_addr_lo(struct ccp_dma_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return lower_32_bits(info->address + info->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static inline u32 ccp_addr_hi(struct ccp_dma_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return upper_32_bits(info->address + info->offset) & 0x0000ffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * descriptor for version 5 CPP commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * 8 32-bit words:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * word 0: function; engine; control bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * word 1: length of source data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * word 2: low 32 bits of source pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * word 3: upper 16 bits of source pointer; source memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * word 4: low 32 bits of destination pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * word 5: upper 16 bits of destination pointer; destination memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * word 6: low 32 bits of key pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * word 7: upper 16 bits of key pointer; key memory type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct dword0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unsigned int soc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) unsigned int ioc:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) unsigned int rsvd1:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned int init:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) unsigned int eom:1; /* AES/SHA only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned int function:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) unsigned int engine:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) unsigned int prot:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned int rsvd2:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct dword3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned int src_hi:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) unsigned int src_mem:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) unsigned int lsb_cxt_id:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned int rsvd1:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned int fixed:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) union dword4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) u32 dst_lo; /* NON-SHA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u32 sha_len_lo; /* SHA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) union dword5 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) unsigned int dst_hi:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) unsigned int dst_mem:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned int rsvd1:13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) unsigned int fixed:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) } fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u32 sha_len_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct dword7 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) unsigned int key_hi:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) unsigned int key_mem:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) unsigned int rsvd1:14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct ccp5_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct dword0 dw0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u32 src_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct dword3 dw3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) union dword4 dw4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) union dword5 dw5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u32 key_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct dword7 dw7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) void ccp_add_device(struct ccp_device *ccp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) void ccp_del_device(struct ccp_device *ccp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) extern void ccp_log_error(struct ccp_device *, unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct ccp_device *ccp_alloc_struct(struct sp_device *sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) bool ccp_queues_suspended(struct ccp_device *ccp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int ccp_cmd_queue_thread(void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int ccp_trng_read(struct hwrng *rng, void *data, size_t max, bool wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int ccp_run_cmd(struct ccp_cmd_queue *cmd_q, struct ccp_cmd *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int ccp_register_rng(struct ccp_device *ccp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) void ccp_unregister_rng(struct ccp_device *ccp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) int ccp_dmaengine_register(struct ccp_device *ccp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) void ccp_dmaengine_unregister(struct ccp_device *ccp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) void ccp5_debugfs_setup(struct ccp_device *ccp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) void ccp5_debugfs_destroy(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Structure for computation functions that are device-specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct ccp_actions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int (*aes)(struct ccp_op *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int (*xts_aes)(struct ccp_op *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int (*des3)(struct ccp_op *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) int (*sha)(struct ccp_op *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int (*rsa)(struct ccp_op *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) int (*passthru)(struct ccp_op *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int (*ecc)(struct ccp_op *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u32 (*sballoc)(struct ccp_cmd_queue *, unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) void (*sbfree)(struct ccp_cmd_queue *, unsigned int, unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) unsigned int (*get_free_slots)(struct ccp_cmd_queue *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) int (*init)(struct ccp_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) void (*destroy)(struct ccp_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) irqreturn_t (*irqhandler)(int, void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) extern const struct ccp_vdata ccpv3_platform;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) extern const struct ccp_vdata ccpv3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) extern const struct ccp_vdata ccpv5a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) extern const struct ccp_vdata ccpv5b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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