^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Cavium, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __CPTVF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __CPTVF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "cpt_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* Default command queue length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CPT_CMD_QLEN 2046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CPT_CMD_QCHUNK_SIZE 1023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Default command timeout in seconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CPT_COMMAND_TIMEOUT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CPT_TIMER_THOLD 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CPT_NUM_QS_PER_VF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CPT_INST_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CPT_NEXT_CHUNK_PTR_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CPT_VF_MSIX_VECTORS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CPT_VF_INTR_MBOX_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CPT_VF_INTR_DOVF_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CPT_VF_INTR_IRDE_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CPT_VF_INTR_NWRP_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CPT_VF_INTR_SERR_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DMA_DIRECT_DIRECT 0 /* Input DIRECT, Output DIRECT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DMA_GATHER_SCATTER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FROM_DPTR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Enumeration cpt_vf_int_vec_e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * CPT VF MSI-X Vector Enumeration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Enumerates the MSI-X interrupt vectors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) enum cpt_vf_int_vec_e {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) CPT_VF_INT_VEC_E_MISC = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) CPT_VF_INT_VEC_E_DONE = 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct command_chunk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u8 *head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 size; /* Chunk size, max CPT_INST_CHUNK_MAX_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct hlist_node nextchunk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct command_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) spinlock_t lock; /* command queue lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 idx; /* Command queue host write idx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 nchunks; /* Number of command chunks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct command_chunk *qhead; /* Command queue head, instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * are inserted here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct hlist_head chead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct command_qinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 cmd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 qchunksize; /* Command queue chunk size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct command_queue queue[CPT_NUM_QS_PER_VF];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct pending_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 busy; /* Entry status (free/busy) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) volatile u64 *completion_addr; /* Completion address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void *post_arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void (*callback)(int, void *); /* Kernel ASYNC request callabck */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void *callback_arg; /* Kernel ASYNC request callabck arg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct pending_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct pending_entry *head; /* head of the queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 front; /* Process work from here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 rear; /* Append new work here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) atomic64_t pending_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) spinlock_t lock; /* Queue lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct pending_qinfo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 nr_queues; /* Number of queues supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 qlen; /* Queue length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct pending_queue queue[CPT_NUM_QS_PER_VF];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define for_each_pending_queue(qinfo, q, i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) for (i = 0, q = &qinfo->queue[i]; i < qinfo->nr_queues; i++, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) q = &qinfo->queue[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct cpt_vf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u16 flags; /* Flags to hold device status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 vfid; /* Device Index 0...CPT_MAX_VF_NUM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 vftype; /* VF type of SE_TYPE(1) or AE_TYPE(1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 vfgrp; /* VF group (0 - 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 node; /* Operating node: Bits (46:44) in BAR0 address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 priority; /* VF priority ring: 1-High proirity round
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * robin ring;0-Low priority round robin ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct pci_dev *pdev; /* pci device handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void __iomem *reg_base; /* Register start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void *wqe_info; /* BH worker info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* MSI-X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) cpumask_var_t affinity_mask[CPT_VF_MSIX_VECTORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Command and Pending queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 qsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 nr_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct command_qinfo cqinfo; /* Command queue information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct pending_qinfo pqinfo; /* Pending queue information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* VF-PF mailbox communication */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bool pf_acked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bool pf_nacked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int cptvf_send_vf_up(struct cpt_vf *cptvf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int cptvf_send_vf_down(struct cpt_vf *cptvf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int cptvf_send_vf_priority_msg(struct cpt_vf *cptvf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int cptvf_send_vq_size_msg(struct cpt_vf *cptvf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int cptvf_check_pf_ready(struct cpt_vf *cptvf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void cptvf_handle_mbox_intr(struct cpt_vf *cptvf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void cvm_crypto_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int cvm_crypto_init(struct cpt_vf *cptvf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void vq_post_process(struct cpt_vf *cptvf, u32 qno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void cptvf_write_vq_doorbell(struct cpt_vf *cptvf, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif /* __CPTVF_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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