Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2016 Cavium, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __CPTPF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __CPTPF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "cpt_common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CSR_DELAY 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CPT_MAX_CORE_GROUPS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CPT_MAX_SE_CORES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CPT_MAX_AE_CORES 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CPT_MAX_TOTAL_CORES (CPT_MAX_SE_CORES + CPT_MAX_AE_CORES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CPT_MAX_VF_NUM 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define	CPT_PF_MSIX_VECTORS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CPT_PF_INT_VEC_E_MBOXX(a) (0x02 + (a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CPT_UCODE_VERSION_SZ 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct cpt_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct microcode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	u8 is_mc_valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	u8 is_ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	u8 group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	u8 num_cores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	u32 code_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	u64 core_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	u8 version[CPT_UCODE_VERSION_SZ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	/* Base info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	dma_addr_t phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	void *code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct cpt_vf_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	u8 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	u8 priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	u32 qlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  * cpt device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct cpt_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	u16 flags;	/* Flags to hold device status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	u8 num_vf_en; /* Number of VFs enabled (0...CPT_MAX_VF_NUM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	struct cpt_vf_info vfinfo[CPT_MAX_VF_NUM]; /* Per VF info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	void __iomem *reg_base; /* Register start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	struct pci_dev *pdev; /* pci device handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	struct microcode mcode[CPT_MAX_CORE_GROUPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	u8 next_mc_idx; /* next microcode index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	u8 next_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	u8 max_se_cores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	u8 max_ae_cores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void cpt_mbox_intr_handler(struct cpt_device *cpt, int mbx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif /* __CPTPF_H */