^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * CAAM hardware register-level view
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2008-2011 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io-64-nonatomic-hi-lo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Architecture-specific register access methods
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * CAAM's bus-addressable registers are 64 bits internally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * They have been wired to be safely accessible on 32-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * architectures, however. Registers were organized such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * that (a) they can be contained in 32 bits, (b) if not, then they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * can be treated as two 32-bit entities, or finally (c) if they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * must be treated as a single 64-bit value, then this can safely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * be done with two 32-bit cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * For 32-bit operations on 64-bit values, CAAM follows the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 64-bit register access conventions as it's predecessors, in that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * writes are "triggered" by a write to the register at the numerically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * higher address, thus, a full 64-bit write cycle requires a write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * to the lower address, followed by a write to the higher address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * which will latch/execute the write cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * For example, let's assume a SW reset of CAAM through the master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * configuration register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * - SWRST is in bit 31 of MCFG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * - MCFG begins at base+0x0000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * (and on Power, the convention is 0-31, 32-63, I know...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Assuming a 64-bit write to this MCFG to perform a software reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * would then require a write of 0 to base+0x0000, followed by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * write of 0x80000000 to base+0x0004, which would "execute" the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Of course, since MCFG 63-32 is all zero, we could cheat and simply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * write 0x8000000 to base+0x0004, and the reset would work fine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * However, since CAAM does contain some write-and-read-intended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 64-bit registers, this code defines 64-bit access methods for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * the sake of internal consistency and simplicity, and so that a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * clean transition to 64-bit is possible when it becomes necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * There are limitations to this that the developer must recognize.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 32-bit architectures cannot enforce an atomic-64 operation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Therefore:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * - On writes, since the HW is assumed to latch the cycle on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * write of the higher-numeric-address word, then ordered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * writes work OK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * - For reads, where a register contains a relevant value of more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * that 32 bits, the hardware employs logic to latch the other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * "half" of the data until read, ensuring an accurate value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * This is of particular relevance when dealing with CAAM's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * performance counters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) extern bool caam_little_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) extern bool caam_imx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) extern size_t caam_ptr_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define caam_to_cpu(len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static inline u##len caam##len ## _to_cpu(u##len val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (caam_little_end) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return le##len ## _to_cpu((__force __le##len)val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return be##len ## _to_cpu((__force __be##len)val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define cpu_to_caam(len) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline u##len cpu_to_caam##len(u##len val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (caam_little_end) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return (__force u##len)cpu_to_le##len(val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return (__force u##len)cpu_to_be##len(val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) caam_to_cpu(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) caam_to_cpu(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) caam_to_cpu(64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) cpu_to_caam(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) cpu_to_caam(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) cpu_to_caam(64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline void wr_reg32(void __iomem *reg, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (caam_little_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) iowrite32(data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) iowrite32be(data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline u32 rd_reg32(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (caam_little_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return ioread32be(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (caam_little_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) iowrite32((ioread32(reg) & ~clear) | set, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) iowrite32be((ioread32be(reg) & ~clear) | set, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * The only users of these wr/rd_reg64 functions is the Job Ring (JR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * The DMA address registers in the JR are handled differently depending on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * platform:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * 1. All BE CAAM platforms and i.MX platforms (LE CAAM):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * base + 0x0000 : most-significant 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * base + 0x0004 : least-significant 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * The 32-bit version of this core therefore has to write to base + 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * to set the 32-bit wide DMA address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * 2. All other LE CAAM platforms (LS1021A etc.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * base + 0x0000 : least-significant 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * base + 0x0004 : most-significant 32 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline void wr_reg64(void __iomem *reg, u64 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (caam_little_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (caam_imx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) iowrite32(data >> 32, (u32 __iomem *)(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) iowrite32(data, (u32 __iomem *)(reg) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) iowrite64(data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) iowrite64be(data, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static inline u64 rd_reg64(void __iomem *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (caam_little_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (caam_imx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 low, high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) high = ioread32(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) low = ioread32(reg + sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return low + ((u64)high << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return ioread64(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ioread64be(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static inline u64 cpu_to_caam_dma64(dma_addr_t value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (caam_imx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u64 ret_val = (u64)cpu_to_caam32(lower_32_bits(value)) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret_val |= (u64)cpu_to_caam32(upper_32_bits(value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return ret_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return cpu_to_caam64(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static inline u64 caam_dma64_to_cpu(u64 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (caam_imx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) (u64)caam32_to_cpu(upper_32_bits(value)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return caam64_to_cpu(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline u64 cpu_to_caam_dma(u64 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) caam_ptr_sz == sizeof(u64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return cpu_to_caam_dma64(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return cpu_to_caam32(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static inline u64 caam_dma_to_cpu(u64 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) caam_ptr_sz == sizeof(u64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return caam_dma64_to_cpu(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return caam32_to_cpu(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * jr_outentry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Represents each entry in a JobR output ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static inline void jr_outentry_get(void *outring, int hw_idx, dma_addr_t *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 *jrstatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (caam_ptr_sz == sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 jrstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) } __packed *outentry = outring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) *desc = outentry[hw_idx].desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) *jrstatus = outentry[hw_idx].jrstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dma_addr_t desc;/* Pointer to completed descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 jrstatus; /* Status for completed descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) } __packed *outentry = outring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *desc = outentry[hw_idx].desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *jrstatus = outentry[hw_idx].jrstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SIZEOF_JR_OUTENTRY (caam_ptr_sz + sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static inline dma_addr_t jr_outentry_desc(void *outring, int hw_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dma_addr_t desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) jr_outentry_get(outring, hw_idx, &desc, &unused);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static inline u32 jr_outentry_jrstatus(void *outring, int hw_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dma_addr_t unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 jrstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) jr_outentry_get(outring, hw_idx, &unused, &jrstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return jrstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static inline void jr_inpentry_set(void *inpring, int hw_idx, dma_addr_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (caam_ptr_sz == sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 *inpentry = inpring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) inpentry[hw_idx] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dma_addr_t *inpentry = inpring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) inpentry[hw_idx] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SIZEOF_JR_INPENTRY caam_ptr_sz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Version registers (Era 10+) e80-eff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct version_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 crca; /* CRCA_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 afha; /* AFHA_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 kfha; /* KFHA_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 pkha; /* PKHA_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 aesa; /* AESA_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 mdha; /* MDHA_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 desa; /* DESA_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 snw8a; /* SNW8A_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 snw9a; /* SNW9A_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 zuce; /* ZUCE_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 zuca; /* ZUCA_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 ccha; /* CCHA_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 ptha; /* PTHA_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 rng; /* RNG_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 trng; /* TRNG_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 aaha; /* AAHA_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 rsvd[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 sr; /* SR_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 dma; /* DMA_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 ai; /* AI_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 qi; /* QI_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 jr; /* JR_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 deco; /* DECO_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Version registers bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Number of CHAs instantiated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CHA_VER_NUM_MASK 0xffull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* CHA Miscellaneous Information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CHA_VER_MISC_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CHA_VER_MISC_MASK (0xffull << CHA_VER_MISC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* CHA Revision Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CHA_VER_REV_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define CHA_VER_REV_MASK (0xffull << CHA_VER_REV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* CHA Version ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CHA_VER_VID_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CHA_VER_VID_MASK (0xffull << CHA_VER_VID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* CHA Miscellaneous Information - AESA_MISC specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CHA_VER_MISC_AES_GCM BIT(1 + CHA_VER_MISC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* CHA Miscellaneous Information - PKHA_MISC specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CHA_VER_MISC_PKHA_NO_CRYPT BIT(7 + CHA_VER_MISC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * caam_perfmon - Performance Monitor/Secure Memory Status/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * CAAM Global Status/Component Version IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * Spans f00-fff wherever instantiated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Number of DECOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CHA_NUM_MS_DECONUM_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * CHA version IDs / instantiation bitfields (< Era 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * Defined for use with the cha_id fields in perfmon, but the same shift/mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * selectors can be used to pull out the number of instantiated blocks within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * cha_num fields in perfmon because the locations are the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CHA_ID_LS_AES_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define CHA_ID_LS_DES_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define CHA_ID_LS_ARC4_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define CHA_ID_LS_MD_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define CHA_ID_LS_RNG_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define CHA_ID_LS_SNW8_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define CHA_ID_LS_KAS_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define CHA_ID_LS_PK_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define CHA_ID_MS_CRC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define CHA_ID_MS_SNW9_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define CHA_ID_MS_DECO_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define CHA_ID_MS_JR_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Specific CHA version IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define CHA_VER_VID_AES_LP 0x3ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define CHA_VER_VID_AES_HP 0x4ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define CHA_VER_VID_MD_LP256 0x0ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define CHA_VER_VID_MD_LP512 0x1ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define CHA_VER_VID_MD_HP 0x2ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct sec_vid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u16 ip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u8 maj_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u8 min_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct caam_perfmon {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Performance Monitor Registers f00-f9f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u64 ib_valid_bytes; /* PC_IB_VALIDATED Inbound Bytes Validated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u64 rsvd[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* CAAM Hardware Instantiation Parameters fa0-fbf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define CTPR_MS_QI_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define CTPR_MS_PS BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define CTPR_MS_DPAA2 BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define CTPR_MS_VIRT_EN_INCL 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define CTPR_MS_VIRT_EN_POR 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define CTPR_MS_PG_SZ_MASK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define CTPR_MS_PG_SZ_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u32 comp_parms_ms; /* CTPR - Compile Parameters Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 comp_parms_ls; /* CTPR - Compile Parameters Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u64 rsvd1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* CAAM Global Status fc0-fdf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u64 faultaddr; /* FAR - Fault Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 faultliodn; /* FALR - Fault Address LIODN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 faultdetail; /* FADR - Fault Addr Detail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u32 rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define CSTA_PLEND BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define CSTA_ALT_PLEND BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 status; /* CSTA - CAAM Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u64 rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* Component Instantiation Parameters fe0-fff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u32 rtic_id; /* RVID - RTIC Version ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define CCBVID_ERA_MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define CCBVID_ERA_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 ccb_id; /* CCBVID - CCB Version ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define SECVID_MS_IPID_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define SECVID_MS_IPID_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define SECVID_MS_MAJ_REV_MASK 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define SECVID_MS_MAJ_REV_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* LIODN programming for DMA configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define MSTRID_LOCK_LIODN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define MSTRID_LIODN_MASK 0x0fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct masterid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u32 liodn_ms; /* lock and make-trusted control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u32 liodn_ls; /* LIODN for non-sequence and seq access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Partition ID for DMA configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct partid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u32 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u32 pidr; /* partition ID, DECO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* RNGB test mode (replicated twice in some configurations) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Padded out to 0x100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct rngtst {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u32 mode; /* RTSTMODEx - Test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u32 rsvd1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u32 reset; /* RTSTRESETx - Test reset control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u32 rsvd2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u32 status; /* RTSTSSTATUSx - Test status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u32 rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u32 errstat; /* RTSTERRSTATx - Test error status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u32 rsvd4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u32 errctl; /* RTSTERRCTLx - Test error control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u32 rsvd5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u32 entropy; /* RTSTENTROPYx - Test entropy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u32 rsvd6[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 verifctl; /* RTSTVERIFCTLx - Test verification control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 rsvd7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u32 verifstat; /* RTSTVERIFSTATx - Test verification status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u32 rsvd8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 verifdata; /* RTSTVERIFDx - Test verification data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u32 rsvd9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u32 xkey; /* RTSTXKEYx - Test XKEY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u32 rsvd10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 rsvd11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 oscct; /* RTSTOSCCTx - Test oscillator counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u32 rsvd12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 rsvd13[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u32 rsvd14[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* RNG4 TRNG test registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct rng4tst {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define RTMCTL_ACC BIT(5) /* TRNG access mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define RTMCTL_PRGM BIT(16) /* 1 -> program mode, 0 -> run mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) both entropy shifter and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) statistical checker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) entropy shifter and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) statistical checker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) entropy shifter, raw data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) in statistical checker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u32 rtmctl; /* misc. control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u32 rtscmisc; /* statistical check misc. register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u32 rtpkrrng; /* poker range register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u32 rtpkrmax; /* PRGM=1: poker max. limit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define RTSDCTL_ENT_DLY_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define RTSDCTL_ENT_DLY_MIN 3200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define RTSDCTL_ENT_DLY_MAX 12800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u32 rtsdctl; /* seed control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 rtsblim; /* PRGM=1: sparse bit limit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 rttotsam; /* PRGM=0: total samples register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u32 rtfrqmin; /* frequency count min. limit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define RTFRQMAX_DISABLE (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u32 rtfrqcnt; /* PRGM=0: freq. count register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u32 rsvd1[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define RDSTA_SKVT 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define RDSTA_SKVN 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define RDSTA_PR0 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define RDSTA_PR1 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define RDSTA_IF0 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define RDSTA_IF1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define RDSTA_MASK (RDSTA_PR1 | RDSTA_PR0 | RDSTA_IF1 | RDSTA_IF0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 rdsta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 rsvd2[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * caam_ctrl - basic core configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * starts base + 0x0000 padded out to 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define KEK_KEY_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define TKEK_KEY_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define TDSK_KEY_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define DECO_RESET 1 /* Use with DECO reset/availability regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define DECO_RESET_0 (DECO_RESET << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define DECO_RESET_1 (DECO_RESET << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define DECO_RESET_2 (DECO_RESET << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define DECO_RESET_3 (DECO_RESET << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define DECO_RESET_4 (DECO_RESET << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct caam_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Basic Configuration Section 000-01f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Read/Writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u32 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u32 mcr; /* MCFG Master Config Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u32 rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u32 scfgr; /* SCFGR, Security Config Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* Bus Access Configuration Section 010-11f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Read/Writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u32 rsvd3[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u32 jrstart; /* JRSTART - Job Ring Start Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u32 rsvd4[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 deco_rsr; /* DECORSR - Deco Request Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 rsvd11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u32 deco_rq; /* DECORR - DECO Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u32 rsvd5[22];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* DECO Availability/Reset Section 120-3ff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u32 deco_avail; /* DAR - DECO availability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u32 deco_reset; /* DRR - DECO reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u32 rsvd6[182];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* Key Encryption/Decryption Configuration 400-5ff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Read/Writable only while in Non-secure mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u32 rsvd7[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u64 sknonce; /* SKNR - Secure Key Nonce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u32 rsvd8[70];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* RNG Test/Verification/Debug Access 600-7ff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* (Useful in Test/Debug modes only...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct rngtst rtst[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct rng4tst r4tst[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u32 rsvd9[416];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* Version registers - introduced with era 10 e80-eff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct version_regs vreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Performance Monitor f00-fff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct caam_perfmon perfmon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * Controller master config register defs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define MCFGR_SWRESET 0x80000000 /* software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define MCFGR_DMA_RESET 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define SCFGR_RDBENABLE 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define SCFGR_VIRT_EN 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define DECORSR_JR0 0x00000001 /* JR to supply TZ, SDID, ICID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define DECORSR_VALID 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define DECORR_DEN0 0x00010000 /* DECO0 available for access*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* AXI read cache control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define MCFGR_ARCACHE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define MCFGR_ARCACHE_BUFF (0x1 << MCFGR_ARCACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define MCFGR_ARCACHE_CACH (0x2 << MCFGR_ARCACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define MCFGR_ARCACHE_RALL (0x4 << MCFGR_ARCACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* AXI write cache control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define MCFGR_AWCACHE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define MCFGR_AWCACHE_BUFF (0x1 << MCFGR_AWCACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define MCFGR_AWCACHE_CACH (0x2 << MCFGR_AWCACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define MCFGR_AWCACHE_WALL (0x8 << MCFGR_AWCACHE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* AXI pipeline depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define MCFGR_AXIPIPE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define MCFGR_LARGE_BURST 0x00000004 /* 128/256-byte burst size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define MCFGR_BURST_64 0x00000001 /* 64-byte burst size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* JRSTART register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define JRSTART_JR1_START 0x00000002 /* Start Job ring 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * caam_job_ring - direct job ring setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * 1-4 possible per instantiation, base + 1000/2000/3000/4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * Padded out to 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct caam_job_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* Input ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u64 inpring_base; /* IRBAx - Input desc ring baseaddr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u32 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u32 inpring_size; /* IRSx - Input ring size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) u32 rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u32 inpring_avail; /* IRSAx - Input ring room remaining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u32 rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) u32 inpring_jobadd; /* IRJAx - Input ring jobs added */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* Output Ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) u64 outring_base; /* ORBAx - Output status ring base addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u32 rsvd4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u32 outring_size; /* ORSx - Output ring size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u32 rsvd5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u32 outring_rmvd; /* ORJRx - Output ring jobs removed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u32 rsvd6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u32 outring_used; /* ORSFx - Output ring slots full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Status/Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 rsvd7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u32 jroutstatus; /* JRSTAx - JobR output status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u32 rsvd8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u32 jrintstatus; /* JRINTx - JobR interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u32 rconfig_hi; /* JRxCFG - Ring configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u32 rconfig_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Indices. CAAM maintains as "heads" of each queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u32 rsvd9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u32 inp_rdidx; /* IRRIx - Input ring read index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u32 rsvd10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u32 out_wtidx; /* ORWIx - Output ring write index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Command/control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) u32 rsvd11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u32 jrcommand; /* JRCRx - JobR command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u32 rsvd12[900];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* Version registers - introduced with era 10 e80-eff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct version_regs vreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* Performance Monitor f00-fff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct caam_perfmon perfmon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define JR_RINGSIZE_MASK 0x03ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * jrstatus - Job Ring Output Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * All values in lo word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * Also note, same values written out as status through QI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * in the command/status field of a frame descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define JRSTA_SSRC_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define JRSTA_SSRC_MASK 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define JRSTA_SSRC_NONE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define JRSTA_SSRC_CCB_ERROR 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define JRSTA_SSRC_JUMP_HALT_USER 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define JRSTA_SSRC_DECO 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define JRSTA_SSRC_QI 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define JRSTA_SSRC_JRERROR 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define JRSTA_SSRC_JUMP_HALT_CC 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define JRSTA_DECOERR_JUMP 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define JRSTA_DECOERR_INDEX_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define JRSTA_DECOERR_INDEX_MASK 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define JRSTA_DECOERR_ERROR_MASK 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define JRSTA_DECOERR_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define JRSTA_DECOERR_LINKLEN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define JRSTA_DECOERR_LINKPTR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define JRSTA_DECOERR_JRCTRL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define JRSTA_DECOERR_DESCCMD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define JRSTA_DECOERR_ORDER 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define JRSTA_DECOERR_KEYCMD 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define JRSTA_DECOERR_LOADCMD 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define JRSTA_DECOERR_STORECMD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define JRSTA_DECOERR_OPCMD 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define JRSTA_DECOERR_FIFOLDCMD 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define JRSTA_DECOERR_FIFOSTCMD 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define JRSTA_DECOERR_MOVECMD 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define JRSTA_DECOERR_JUMPCMD 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define JRSTA_DECOERR_MATHCMD 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define JRSTA_DECOERR_SHASHCMD 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define JRSTA_DECOERR_SEQCMD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define JRSTA_DECOERR_DECOINTERNAL 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define JRSTA_DECOERR_SHDESCHDR 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define JRSTA_DECOERR_HDRLEN 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define JRSTA_DECOERR_BURSTER 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define JRSTA_DECOERR_DESCSIGNATURE 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define JRSTA_DECOERR_DMA 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define JRSTA_DECOERR_BURSTFIFO 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define JRSTA_DECOERR_JRRESET 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define JRSTA_DECOERR_JOBFAIL 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define JRSTA_DECOERR_DNRERR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define JRSTA_DECOERR_UNDEFPCL 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define JRSTA_DECOERR_PDBERR 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define JRSTA_DECOERR_ANRPLY_LATE 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define JRSTA_DECOERR_SEQOVF 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define JRSTA_DECOERR_INVSIGN 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define JRSTA_DECOERR_DSASIGN 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define JRSTA_QIERR_ERROR_MASK 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define JRSTA_CCBERR_JUMP 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define JRSTA_CCBERR_INDEX_MASK 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define JRSTA_CCBERR_INDEX_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define JRSTA_CCBERR_CHAID_MASK 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define JRSTA_CCBERR_CHAID_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define JRSTA_CCBERR_ERRID_MASK 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define JRSTA_CCBERR_ERRID_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define JRSTA_CCBERR_ERRID_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define JRSTA_CCBERR_ERRID_DATASIZ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define JRSTA_CCBERR_ERRID_KEYSIZ 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define JRSTA_CCBERR_ERRID_ICVCHK 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define JRSTA_CCBERR_ERRID_CCMAAD 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define JRSTA_CCBERR_ERRID_INVCHA 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define JRINT_ERR_INDEX_MASK 0x3fff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define JRINT_ERR_INDEX_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define JRINT_ERR_TYPE_MASK 0xf00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define JRINT_ERR_TYPE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define JRINT_ERR_HALT_MASK 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define JRINT_ERR_HALT_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define JRINT_ERR_HALT_INPROGRESS 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define JRINT_ERR_HALT_COMPLETE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define JRINT_JR_ERROR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define JRINT_JR_INT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define JRINT_ERR_TYPE_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define JRINT_ERR_TYPE_BAD_INPADDR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define JRINT_ERR_TYPE_BAD_OUTADDR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define JRINT_ERR_TYPE_INV_INPWRT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define JRINT_ERR_TYPE_INV_OUTWRT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define JRINT_ERR_TYPE_RESET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define JRINT_ERR_TYPE_REMOVE_OFL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define JRINT_ERR_TYPE_ADD_OFL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define JRCFG_SOE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define JRCFG_ICEN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define JRCFG_IMSK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define JRCFG_ICDCT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define JRCFG_ICTT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define JRCR_RESET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) * caam_assurance - Assurance Controller View
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) * base + 0x6000 padded out to 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct rtic_element {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) u64 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u32 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct rtic_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) struct rtic_element element[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct rtic_memhash {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u32 memhash_be[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) u32 memhash_le[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct caam_assurance {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* Status/Command/Watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) u32 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u32 status; /* RSTA - Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) u32 rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) u32 cmd; /* RCMD - Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u32 rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) u32 ctrl; /* RCTL - Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u32 rsvd4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) u32 throttle; /* RTHR - Throttle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u32 rsvd5[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u64 watchdog; /* RWDOG - Watchdog Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u32 rsvd6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u32 rend; /* REND - Endian corrections */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) u32 rsvd7[50];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* Block access/configuration @ 100/110/120/130 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct rtic_block memblk[4]; /* Memory Blocks A-D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u32 rsvd8[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* Block hashes @ 200/300/400/500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct rtic_memhash hash[4]; /* Block hash values A-D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u32 rsvd_3[640];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * caam_queue_if - QI configuration and control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * starts base + 0x7000, padded out to 0x1000 long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct caam_queue_if {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u32 qi_control_hi; /* QICTL - QI Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u32 qi_control_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) u32 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) u32 qi_status; /* QISTA - QI Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u32 qi_deq_cfg_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) u32 qi_enq_cfg_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) u32 rsvd2[1016];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /* QI control bits - low word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define QICTL_DQEN 0x01 /* Enable frame pop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define QICTL_STOP 0x02 /* Stop dequeue/enqueue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define QICTL_SOE 0x04 /* Stop on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* QI control bits - high word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define QICTL_MBSI 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define QICTL_MHWSI 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define QICTL_MWSI 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define QICTL_MDWSI 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define QICTL_MBSO 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define QICTL_MHWSO 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define QICTL_MWSO 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define QICTL_MDWSO 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define QICTL_DMBS 0x010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define QICTL_EPO 0x020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* QI status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define QISTA_PHRDERR 0x01 /* PreHeader Read Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define QISTA_OFWRERR 0x04 /* Output Frame Read Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define QISTA_BTSERR 0x10 /* Buffer Undersize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* deco_sg_table - DECO view of scatter/gather table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct deco_sg_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) u64 addr; /* Segment Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) u32 elen; /* E, F bits + 30-bit length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) u32 bpid_offset; /* Buffer Pool ID + 16-bit length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * caam_deco - descriptor controller - CHA cluster block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * Only accessible when direct DECO access is turned on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * (done in DECORR, via MID programmed in DECOxMID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * 5 typical, base + 0x8000/9000/a000/b000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * Padded out to 0x1000 long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) struct caam_deco {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) u32 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) u32 cls1_mode; /* CxC1MR - Class 1 Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) u32 rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) u32 cls1_datasize_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) u32 rsvd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) u32 rsvd4[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) u32 cha_ctrl; /* CCTLR - CHA control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) u32 rsvd5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) u32 rsvd6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) u32 clr_written; /* CxCWR - Clear-Written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) u32 ccb_status_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) u32 rsvd7[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) u32 aad_size; /* CxAADSZR - Current AAD Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) u32 rsvd8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) u32 rsvd9[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) u32 pkha_a_size; /* PKASZRx - Size of PKHA A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) u32 rsvd10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) u32 rsvd11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) u32 rsvd12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) u32 pkha_e_size; /* PKESZRx - Size of PKHA E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) u32 rsvd13[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) u32 rsvd14[48];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u32 rsvd15[121];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) u32 cls2_mode; /* CxC2MR - Class 2 Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) u32 rsvd16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) u32 cls2_datasize_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) u32 rsvd17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) u32 rsvd18[56];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) u32 rsvd19[46];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) u32 rsvd20[84];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) u32 inp_infofifo_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) u32 rsvd21[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) u32 rsvd22[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) u64 out_datafifo; /* CxOFIFO - Output Data FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) u32 rsvd23[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) u32 jr_ctl_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) u32 op_status_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) u32 rsvd24[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) u32 rsvd26[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) u64 math[4]; /* DxMTH - Math register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) u32 rsvd27[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) u32 rsvd28[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) u32 rsvd29[48];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) u32 descbuf[64]; /* DxDESB - Descriptor buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u32 rscvd30[193];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define DESC_DBG_DECO_STAT_VALID 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define DESC_DBG_DECO_STAT_MASK 0x00F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define DESC_DBG_DECO_STAT_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) u32 desc_dbg; /* DxDDR - DECO Debug Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) u32 rsvd31[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define DESC_DER_DECO_STAT_MASK 0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define DESC_DER_DECO_STAT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) u32 dbg_exec; /* DxDER - DECO Debug Exec Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) u32 rsvd32[112];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define DECO_STAT_HOST_ERR 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define DECO_JQCR_WHL 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define DECO_JQCR_FOUR 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define JR_BLOCK_NUMBER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define ASSURE_BLOCK_NUMBER 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define QI_BLOCK_NUMBER 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define DECO_BLOCK_NUMBER 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define PG_SIZE_4K 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define PG_SIZE_64K 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #endif /* REGS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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