^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2013-2016 Freescale Semiconductor Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2017-2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DPSECI_CMD_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DPSECI_CMD_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* DPSECI Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DPSECI_VER_MAJOR 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DPSECI_VER_MINOR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DPSECI_VER(maj, min) (((maj) << 16) | (min))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DPSECI_VERSION DPSECI_VER(DPSECI_VER_MAJOR, DPSECI_VER_MINOR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Command versioning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DPSECI_CMD_BASE_VERSION 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DPSECI_CMD_BASE_VERSION_V2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DPSECI_CMD_ID_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DPSECI_CMD_V1(id) (((id) << DPSECI_CMD_ID_OFFSET) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) DPSECI_CMD_BASE_VERSION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DPSECI_CMD_V2(id) (((id) << DPSECI_CMD_ID_OFFSET) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) DPSECI_CMD_BASE_VERSION_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Command IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DPSECI_CMDID_CLOSE DPSECI_CMD_V1(0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DPSECI_CMDID_OPEN DPSECI_CMD_V1(0x809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DPSECI_CMDID_GET_API_VERSION DPSECI_CMD_V1(0xa09)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DPSECI_CMDID_ENABLE DPSECI_CMD_V1(0x002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DPSECI_CMDID_DISABLE DPSECI_CMD_V1(0x003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DPSECI_CMDID_GET_ATTR DPSECI_CMD_V1(0x004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DPSECI_CMDID_RESET DPSECI_CMD_V1(0x005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DPSECI_CMDID_IS_ENABLED DPSECI_CMD_V1(0x006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DPSECI_CMDID_SET_RX_QUEUE DPSECI_CMD_V1(0x194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DPSECI_CMDID_GET_RX_QUEUE DPSECI_CMD_V1(0x196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DPSECI_CMDID_GET_TX_QUEUE DPSECI_CMD_V1(0x197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DPSECI_CMDID_GET_SEC_ATTR DPSECI_CMD_V2(0x198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DPSECI_CMDID_SET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DPSECI_CMDID_GET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Macros for accessing command fields smaller than 1 byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DPSECI_MASK(field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) GENMASK(DPSECI_##field##_SHIFT + DPSECI_##field##_SIZE - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DPSECI_##field##_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define dpseci_set_field(var, field, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ((var) |= (((val) << DPSECI_##field##_SHIFT) & DPSECI_MASK(field)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define dpseci_get_field(var, field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) (((var) & DPSECI_MASK(field)) >> DPSECI_##field##_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct dpseci_cmd_open {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __le32 dpseci_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DPSECI_ENABLE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DPSECI_ENABLE_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct dpseci_rsp_is_enabled {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 is_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct dpseci_rsp_get_attributes {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __le32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) __le32 pad0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 num_tx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 num_rx_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 pad1[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __le32 options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DPSECI_DEST_TYPE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DPSECI_DEST_TYPE_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DPSECI_ORDER_PRESERVATION_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DPSECI_ORDER_PRESERVATION_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct dpseci_cmd_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __le32 dest_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u8 dest_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __le64 user_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __le32 options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __le32 fqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u8 order_preservation_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct dpseci_rsp_get_tx_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __le32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __le32 fqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u8 priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct dpseci_rsp_get_sec_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __le16 ip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 major_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 minor_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 era;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 pad0[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 deco_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 zuc_auth_acc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 zuc_enc_acc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 snow_f8_acc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 snow_f9_acc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u8 crc_acc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u8 pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u8 pk_acc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 kasumi_acc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 rng_acc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 pad3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u8 md_acc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 arc4_acc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 des_acc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 aes_acc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u8 ccha_acc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 ptha_acc_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct dpseci_rsp_get_api_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) __le16 major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __le16 minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DPSECI_CGN_DEST_TYPE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DPSECI_CGN_DEST_TYPE_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define DPSECI_CGN_UNITS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DPSECI_CGN_UNITS_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct dpseci_cmd_congestion_notification {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) __le32 dest_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) __le16 notification_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u8 options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __le64 message_iova;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) __le64 message_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __le32 threshold_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __le32 threshold_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif /* _DPSECI_CMD_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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