^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* * CAAM control-plane driver backend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Controller-level driver, kernel property detection, initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2008-2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2018-2019 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/fsl/mc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "compat.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "debugfs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "intern.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "jr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "desc_constr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "ctrl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) bool caam_dpaa2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) EXPORT_SYMBOL(caam_dpaa2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifdef CONFIG_CAAM_QI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "qi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Descriptor to instantiate RNG State Handle 0 in normal mode and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * load the JDKEK, TDKEK and TDSK registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 *jump_cmd, op_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) init_job_desc(desc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) OP_ALG_PR_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* INIT RNG in non-test mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) append_operation(desc, op_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (!handle && do_sk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * For SH0, Secure Keys must be generated as well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* wait for done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) set_jump_tgt_here(desc, jump_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * load 1 to clear written reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * resets the done interrupt and returns the RNG to idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Initialize State Handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) OP_ALG_AAI_RNG4_SK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Descriptor for deinstantiation of State Handle 0 of the RNG block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void build_deinstantiation_desc(u32 *desc, int handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) init_job_desc(desc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Uninstantiate State Handle 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * the software (no JR/QI used).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @ctrldev - pointer to device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @status - descriptor status, after being run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Return: - 0 if no error occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * - -ENODEV if the DECO couldn't be acquired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * - -EAGAIN if an error occurred while executing the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct caam_deco __iomem *deco = ctrlpriv->deco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int timeout = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 deco_dbg_reg, deco_state, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ctrlpriv->virt_en == 1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Apparently on i.MX8M{Q,M,N,P} it doesn't matter if virt_en == 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * and the following steps should be performed regardless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) of_machine_is_compatible("fsl,imx8mq") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) of_machine_is_compatible("fsl,imx8mm") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) of_machine_is_compatible("fsl,imx8mn") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) of_machine_is_compatible("fsl,imx8mp")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) --timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) timeout = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) --timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev_err(ctrldev, "failed to acquire DECO 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) for (i = 0; i < desc_len(desc); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) flags = DECO_JQCR_WHL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * If the descriptor length is longer than 4 words, then the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * FOUR bit in JRCTRL register must be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (desc_len(desc) >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) flags |= DECO_JQCR_FOUR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Instruct the DECO to execute it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) timeout = 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) deco_dbg_reg = rd_reg32(&deco->desc_dbg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (ctrlpriv->era < 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) deco_state = (deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DESC_DBG_DECO_STAT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) deco_state = (rd_reg32(&deco->dbg_exec) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DESC_DER_DECO_STAT_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DESC_DER_DECO_STAT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * If an error occurred in the descriptor, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * the DECO status field will be set to 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (deco_state == DECO_STAT_HOST_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) *status = rd_reg32(&deco->op_status_hi) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DECO_OP_STATUS_HI_ERR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ctrlpriv->virt_en == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Mark the DECO as free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * deinstantiate_rng - builds and executes a descriptor on DECO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * which deinitializes the RNG block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @ctrldev - pointer to device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @state_handle_mask - bitmask containing the instantiation status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * for the RNG4 state handles which exist in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * the RNG4 block: 1 if it's been instantiated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Return: - 0 if no error occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * - -ENOMEM if there isn't enough memory to allocate the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * - -ENODEV if DECO0 couldn't be acquired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * - -EAGAIN if an error occurred when executing the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 *desc, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int sh_idx, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * If the corresponding bit is set, then it means the state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * handle was initialized by us, and thus it needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * deinitialized as well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if ((1 << sh_idx) & state_handle_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Create the descriptor for deinstantating this state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) build_deinstantiation_desc(desc, sh_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Try to run it through DECO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ret = run_descriptor_deco0(ctrldev, desc, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_err(ctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "Failed to deinstantiate RNG4 SH%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) sh_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void devm_deinstantiate_rng(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct device *ctrldev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * De-initialize RNG state handles initialized by this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * In case of SoCs with Management Complex, RNG is managed by MC f/w.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (ctrlpriv->rng4_sh_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * instantiate_rng - builds and executes a descriptor on DECO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * which initializes the RNG block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @ctrldev - pointer to device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @state_handle_mask - bitmask containing the instantiation status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * for the RNG4 state handles which exist in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * the RNG4 block: 1 if it's been instantiated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * by an external entry, 0 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * Caution: this can be done only once; if the keys need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * regenerated, a POR is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * Return: - 0 if no error occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * - -ENOMEM if there isn't enough memory to allocate the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * - -ENODEV if DECO0 couldn't be acquired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * - -EAGAIN if an error occurred when executing the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * f.i. there was a RNG hardware error due to not "good enough"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * entropy being acquired.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int gen_sk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct caam_ctrl __iomem *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 *desc, status = 0, rdsta_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int ret = 0, sh_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) const u32 rdsta_if = RDSTA_IF0 << sh_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) const u32 rdsta_pr = RDSTA_PR0 << sh_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) const u32 rdsta_mask = rdsta_if | rdsta_pr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * If the corresponding bit is set, this state handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * was initialized by somebody else, so it's left alone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (rdsta_if & state_handle_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (rdsta_pr & state_handle_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_info(ctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "RNG4 SH%d was previously instantiated without prediction resistance. Tearing it down\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) sh_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = deinstantiate_rng(ctrldev, rdsta_if);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Create the descriptor for instantiating RNG State Handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) build_instantiation_desc(desc, sh_idx, gen_sk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Try to run it through DECO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = run_descriptor_deco0(ctrldev, desc, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * If ret is not 0, or descriptor status is not 0, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * something went wrong. No need to try the next state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * handle (if available), bail out here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * Also, if for some reason, the State Handle didn't get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * instantiated although the descriptor has finished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * without any error (HW optimizations for later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * CAAM eras), then try again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) (rdsta_val & rdsta_mask) != rdsta_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Clear the contents before recreating the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) memset(desc, 0x00, CAAM_CMD_SZ * 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return devm_add_action_or_reset(ctrldev, devm_deinstantiate_rng, ctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * kick_trng - sets the various parameters for enabling the initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * of the RNG4 block in CAAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * @pdev - pointer to the platform device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @ent_delay - Defines the length (in system clocks) of each entropy sample.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static void kick_trng(struct platform_device *pdev, int ent_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct device *ctrldev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct caam_ctrl __iomem *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct rng4tst __iomem *r4tst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) r4tst = &ctrl->r4tst[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * properly invalidate the entropy in the entropy register and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * force re-generation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM | RTMCTL_ACC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * Performance-wise, it does not make sense to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * set the delay to a value that is lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * than the last one that worked (i.e. the state handles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * were instantiated properly. Thus, instead of wasting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * time trying to set the values controlling the sample
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * frequency, the function simply returns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) >> RTSDCTL_ENT_DLY_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ent_delay <= val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) goto start_rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) val = rd_reg32(&r4tst->rtsdctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) val = (val & ~RTSDCTL_ENT_DLY_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) wr_reg32(&r4tst->rtsdctl, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* min. freq. count, equal to 1/4 of the entropy sample length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* disable maximum frequency count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* read the control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) val = rd_reg32(&r4tst->rtmctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) start_rng:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * select raw sampling in both entropy shifter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * and statistical checker; ; put RNG4 into run mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM | RTMCTL_ACC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) RTMCTL_SAMP_MODE_RAW_ES_SC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u16 ip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u8 maj_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u8 era;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) } id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x0A10, 1, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x0A10, 2, 2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x0A12, 1, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x0A14, 1, 3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x0A14, 2, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x0A16, 1, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x0A10, 3, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x0A11, 1, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x0A18, 1, 4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x0A11, 2, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x0A12, 2, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x0A13, 1, 5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x0A1C, 1, 5}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 ccbvid, id_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u8 maj_rev, era;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u16 ip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ccbvid = rd_reg32(&ctrl->perfmon.ccb_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (era) /* This is '0' prior to CAAM ERA-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return era;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) for (i = 0; i < ARRAY_SIZE(id); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return id[i].era;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * caam_get_era() - Return the ERA of the SEC on SoC, based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * on "sec-era" optional property in the DTS. This property is updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * by u-boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * In case this property is not passed an attempt to retrieve the CAAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * era via register reads will be made.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * @ctrl: controller region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int caam_get_era(struct caam_ctrl __iomem *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct device_node *caam_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u32 prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) of_node_put(caam_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return caam_get_era_from_hw(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * ERRATA: imx6 devices (imx6D, imx6Q, imx6DL, imx6S, imx6DP and imx6QP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * have an issue wherein AXI bus transactions may not occur in the correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * order. This isn't a problem running single descriptors, but can be if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * running multiple concurrent descriptors. Reworking the driver to throttle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * to single requests is impractical, thus the workaround is to limit the AXI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * pipeline to a depth of 1 (from it's default of 4) to preclude this situation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * from occurring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static void handle_imx6_err005766(u32 __iomem *mcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (of_machine_is_compatible("fsl,imx6q") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) of_machine_is_compatible("fsl,imx6dl") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) of_machine_is_compatible("fsl,imx6qp"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) clrsetbits_32(mcr, MCFGR_AXIPIPE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 1 << MCFGR_AXIPIPE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const struct of_device_id caam_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .compatible = "fsl,sec-v4.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .compatible = "fsl,sec4.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) MODULE_DEVICE_TABLE(of, caam_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct caam_imx_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) const struct clk_bulk_data *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static const struct clk_bulk_data caam_imx6_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) { .id = "ipg" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) { .id = "mem" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) { .id = "aclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) { .id = "emi_slow" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const struct caam_imx_data caam_imx6_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .clks = caam_imx6_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .num_clks = ARRAY_SIZE(caam_imx6_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const struct clk_bulk_data caam_imx7_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) { .id = "ipg" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) { .id = "aclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct caam_imx_data caam_imx7_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .clks = caam_imx7_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .num_clks = ARRAY_SIZE(caam_imx7_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const struct clk_bulk_data caam_imx6ul_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { .id = "ipg" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { .id = "mem" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) { .id = "aclk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static const struct caam_imx_data caam_imx6ul_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .clks = caam_imx6ul_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .num_clks = ARRAY_SIZE(caam_imx6ul_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const struct clk_bulk_data caam_vf610_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) { .id = "ipg" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static const struct caam_imx_data caam_vf610_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .clks = caam_vf610_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .num_clks = ARRAY_SIZE(caam_vf610_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const struct soc_device_attribute caam_imx_soc_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) { .soc_id = "i.MX6UL", .data = &caam_imx6ul_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { .soc_id = "i.MX6*", .data = &caam_imx6_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) { .soc_id = "i.MX7*", .data = &caam_imx7_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) { .soc_id = "i.MX8M*", .data = &caam_imx7_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) { .soc_id = "VF*", .data = &caam_vf610_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) { .family = "Freescale i.MX" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static void disable_clocks(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct caam_drv_private *ctrlpriv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) clk_bulk_disable_unprepare(ctrlpriv->num_clks, ctrlpriv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int init_clocks(struct device *dev, const struct caam_imx_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ctrlpriv->num_clks = data->num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ctrlpriv->clks = devm_kmemdup(dev, data->clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) data->num_clks * sizeof(data->clks[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (!ctrlpriv->clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = devm_clk_bulk_get(dev, ctrlpriv->num_clks, ctrlpriv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) "Failed to request all necessary clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ret = clk_bulk_prepare_enable(ctrlpriv->num_clks, ctrlpriv->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) "Failed to prepare/enable all necessary clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return devm_add_action_or_reset(dev, disable_clocks, ctrlpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static void caam_remove_debugfs(void *root)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) debugfs_remove_recursive(root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #ifdef CONFIG_FSL_MC_BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static bool check_version(struct fsl_mc_version *mc_version, u32 major,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 minor, u32 revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (mc_version->major > major)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (mc_version->major == major) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (mc_version->minor > minor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (mc_version->minor == minor &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) mc_version->revision > revision)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Probe routine for CAAM top (controller) level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static int caam_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u64 caam_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) const struct soc_device_attribute *imx_soc_match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct device_node *nprop, *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct caam_ctrl __iomem *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct caam_drv_private *ctrlpriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct dentry *dfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u32 scfgr, comp_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u8 rng_vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int pg_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int BLOCK_OFFSET = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) bool pr_support = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (!ctrlpriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev_set_drvdata(dev, ctrlpriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) nprop = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) imx_soc_match = soc_device_match(caam_imx_soc_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) caam_imx = (bool)imx_soc_match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (imx_soc_match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (!imx_soc_match->data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dev_err(dev, "No clock data provided for i.MX SoC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ret = init_clocks(dev, imx_soc_match->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Get configuration properties from device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* First, get register page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ctrl = devm_of_iomap(dev, nprop, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = PTR_ERR_OR_ZERO(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dev_err(dev, "caam: of_iomap() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) (CSTA_PLEND | CSTA_ALT_PLEND));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) caam_ptr_sz = sizeof(u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) caam_ptr_sz = sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #ifdef CONFIG_CAAM_QI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* If (DPAA 1.x) QI present, check whether dependencies are available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (ctrlpriv->qi_present && !caam_dpaa2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ret = qman_is_probed();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) } else if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_err(dev, "failing probe due to qman probe error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ret = qman_portals_probed();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) } else if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev_err(dev, "failing probe due to qman portals probe error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Allocating the BLOCK_OFFSET based on the supported page size on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * the platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (pg_size == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) BLOCK_OFFSET = PG_SIZE_4K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) BLOCK_OFFSET = PG_SIZE_64K;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ctrlpriv->assure = (struct caam_assurance __iomem __force *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ((__force uint8_t *)ctrl +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ctrlpriv->deco = (struct caam_deco __iomem __force *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ((__force uint8_t *)ctrl +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) BLOCK_OFFSET * DECO_BLOCK_NUMBER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Get the IRQ of the controller (for security violations only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ctrlpriv->mc_en = !!np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #ifdef CONFIG_FSL_MC_BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (ctrlpriv->mc_en) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct fsl_mc_version *mc_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) mc_version = fsl_mc_get_version();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (mc_version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) pr_support = check_version(mc_version, 10, 20, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * long pointers in master configuration register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * In case of SoCs with Management Complex, MC f/w performs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * the configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (!ctrlpriv->mc_en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) MCFGR_WDENABLE | MCFGR_LARGE_BURST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) handle_imx6_err005766(&ctrl->mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * Read the Compile Time parameters and SCFGR to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * if virtualization is enabled for this platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) scfgr = rd_reg32(&ctrl->scfgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ctrlpriv->virt_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (comp_params & CTPR_MS_VIRT_EN_INCL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) (scfgr & SCFGR_VIRT_EN)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ctrlpriv->virt_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (comp_params & CTPR_MS_VIRT_EN_POR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ctrlpriv->virt_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (ctrlpriv->virt_en == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) JRSTART_JR1_START | JRSTART_JR2_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) JRSTART_JR3_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ret = dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ctrlpriv->era = caam_get_era(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ctrlpriv->domain = iommu_get_domain_for_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dfs_root = debugfs_create_dir(dev_name(dev), NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (IS_ENABLED(CONFIG_DEBUG_FS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ret = devm_add_action_or_reset(dev, caam_remove_debugfs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dfs_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) caam_debugfs_init(ctrlpriv, dfs_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Check to see if (DPAA 1.x) QI present. If so, enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (ctrlpriv->qi_present && !caam_dpaa2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ((__force uint8_t *)ctrl +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) BLOCK_OFFSET * QI_BLOCK_NUMBER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* This is all that's required to physically enable QI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* If QMAN driver is present, init CAAM-QI backend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #ifdef CONFIG_CAAM_QI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ret = caam_qi_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dev_err(dev, "caam qi i/f init failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ring = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) for_each_available_child_of_node(nprop, np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ((__force uint8_t *)ctrl +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) (ring + JR_BLOCK_NUMBER) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) BLOCK_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ctrlpriv->total_jobrs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ring++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* If no QI and no rings specified, quit and go home */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) dev_err(dev, "no queues configured, terminating\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (ctrlpriv->era < 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) rng_vid = (rd_reg32(&ctrl->perfmon.cha_id_ls) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) CHA_VER_VID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * If SEC has RNG version >= 4 and RNG state handle has not been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * already instantiated, do RNG instantiation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * In case of SoCs with Management Complex, RNG is managed by MC f/w.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (!(ctrlpriv->mc_en && pr_support) && rng_vid >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ctrlpriv->rng4_sh_init =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) rd_reg32(&ctrl->r4tst[0].rdsta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * If the secure keys (TDKEK, JDKEK, TDSK), were already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * generated, signal this to the function that is instantiating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * the state handles. An error would occur if RNG4 attempts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * to regenerate these keys before the next POR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ctrlpriv->rng4_sh_init &= RDSTA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) int inst_handles =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) rd_reg32(&ctrl->r4tst[0].rdsta) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) RDSTA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * If either SH were instantiated by somebody else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * (e.g. u-boot) then it is assumed that the entropy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * parameters are properly set and thus the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * setting these (kick_trng(...)) is skipped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * Also, if a handle was instantiated, do not change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * the TRNG parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) "Entropy delay = %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ent_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) kick_trng(pdev, ent_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ent_delay += 400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * if instantiate_rng(...) fails, the loop will rerun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * and the kick_trng(...) function will modify the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * upper and lower limits of the entropy sampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * interval, leading to a successful initialization of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * the RNG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ret = instantiate_rng(dev, inst_handles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) gen_sk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (ret == -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * if here, the loop will rerun,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * so don't hog the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) dev_err(dev, "failed to instantiate RNG");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * Set handles initialized by this module as the complement of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * the already initialized ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* Enable RDB bit so that RNG works faster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* NOTE: RTIC detection ought to go here, around Si time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* Report "alive" for developer to see */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ctrlpriv->era);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) dev_info(dev, "job rings = %d, qi = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ctrlpriv->total_jobrs, ctrlpriv->qi_present);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ret = devm_of_platform_populate(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) dev_err(dev, "JR platform devices creation error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static struct platform_driver caam_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .name = "caam",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .of_match_table = caam_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .probe = caam_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) module_platform_driver(caam_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) MODULE_DESCRIPTION("FSL CAAM request backend");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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