^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * caam - Freescale FSL CAAM support for Public Key Cryptography descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * There is no Shared Descriptor for PKC so that the Job Descriptor must carry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * all the desired key parameters, input and output pointers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _PKC_DESC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _PKC_DESC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "compat.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "pdb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <crypto/engine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * caam_priv_key_form - CAAM RSA private key representation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * CAAM RSA private key may have either of three forms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * 1. The first representation consists of the pair (n, d), where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * components have the following meanings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * n the RSA modulus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * d the RSA private exponent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 2. The second representation consists of the triplet (p, q, d), where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * components have the following meanings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * p the first prime factor of the RSA modulus n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * q the second prime factor of the RSA modulus n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * d the RSA private exponent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * 3. The third representation consists of the quintuple (p, q, dP, dQ, qInv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * where the components have the following meanings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * p the first prime factor of the RSA modulus n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * q the second prime factor of the RSA modulus n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * dP the first factors's CRT exponent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * dQ the second factors's CRT exponent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * qInv the (first) CRT coefficient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * The benefit of using the third or the second key form is lower computational
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * cost for the decryption and signature operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum caam_priv_key_form {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) FORM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) FORM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) FORM3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * caam_rsa_key - CAAM RSA key structure. Keys are allocated in DMA zone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @n : RSA modulus raw byte stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @e : RSA public exponent raw byte stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @d : RSA private exponent raw byte stream
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @p : RSA prime factor p of RSA modulus n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @q : RSA prime factor q of RSA modulus n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @dp : RSA CRT exponent of p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @dp : RSA CRT exponent of q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @qinv : RSA CRT coefficient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @tmp1 : CAAM uses this temporary buffer as internal state buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * It is assumed to be as long as p.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @tmp2 : CAAM uses this temporary buffer as internal state buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * It is assumed to be as long as q.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @n_sz : length in bytes of RSA modulus n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @e_sz : length in bytes of RSA public exponent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @d_sz : length in bytes of RSA private exponent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @p_sz : length in bytes of RSA prime factor p of RSA modulus n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @q_sz : length in bytes of RSA prime factor q of RSA modulus n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @priv_form : CAAM RSA private key representation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct caam_rsa_key {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 *q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 *dq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 *qinv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u8 *tmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u8 *tmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) size_t n_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) size_t e_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) size_t d_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) size_t p_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) size_t q_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) enum caam_priv_key_form priv_form;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * caam_rsa_ctx - per session context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @enginectx : crypto engine context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @key : RSA key in DMA zone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @dev : device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @padding_dma : dma address of padding, for adding it to the input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct caam_rsa_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct crypto_engine_ctx enginectx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct caam_rsa_key key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dma_addr_t padding_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * caam_rsa_req_ctx - per request context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @src : input scatterlist (stripped of leading zeros)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @fixup_src : input scatterlist (that might be stripped of leading zeros)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @fixup_src_len : length of the fixup_src input scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @edesc : s/w-extended rsa descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @akcipher_op_done : callback used when operation is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct caam_rsa_req_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct scatterlist src[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct scatterlist *fixup_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int fixup_src_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct rsa_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void (*akcipher_op_done)(struct device *jrdev, u32 *desc, u32 err,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void *context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * rsa_edesc - s/w-extended rsa descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @src_nents : number of segments in input s/w scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @dst_nents : number of segments in output s/w scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @mapped_src_nents: number of segments in input h/w link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @mapped_dst_nents: number of segments in output h/w link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @sec4_sg_bytes : length of h/w link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @bklog : stored to determine if the request needs backlog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @sec4_sg_dma : dma address of h/w link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @sec4_sg : pointer to h/w link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @pdb : specific RSA Protocol Data Block (PDB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @hw_desc : descriptor followed by link tables if any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct rsa_edesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int dst_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int mapped_src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int mapped_dst_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int sec4_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) bool bklog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dma_addr_t sec4_sg_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct sec4_sg_entry *sec4_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct rsa_pub_pdb pub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct rsa_priv_f1_pdb priv_f1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct rsa_priv_f2_pdb priv_f2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct rsa_priv_f3_pdb priv_f3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) } pdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 hw_desc[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Descriptor construction primitives. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void init_rsa_pub_desc(u32 *desc, struct rsa_pub_pdb *pdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) void init_rsa_priv_f1_desc(u32 *desc, struct rsa_priv_f1_pdb *pdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) void init_rsa_priv_f2_desc(u32 *desc, struct rsa_priv_f2_pdb *pdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void init_rsa_priv_f3_desc(u32 *desc, struct rsa_priv_f3_pdb *pdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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