Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2015-2016 Freescale Semiconductor Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright 2017-2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _CAAMALG_QI2_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _CAAMALG_QI2_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <soc/fsl/dpaa2-io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <soc/fsl/dpaa2-fd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/threads.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "dpseci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "desc_constr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <crypto/skcipher.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define DPAA2_CAAM_STORE_SIZE	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* NAPI weight *must* be a multiple of the store size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DPAA2_CAAM_NAPI_WEIGHT	512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* The congestion entrance threshold was chosen so that on LS2088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * we support the maximum throughput for the available memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DPAA2_SEC_CONG_ENTRY_THRESH	(128 * 1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DPAA2_SEC_CONG_EXIT_THRESH	(DPAA2_SEC_CONG_ENTRY_THRESH * 9 / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * dpaa2_caam_priv - driver private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * @dpseci_id: DPSECI object unique ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * @major_ver: DPSECI major version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * @minor_ver: DPSECI minor version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * @dpseci_attr: DPSECI attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * @sec_attr: SEC engine attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * @rx_queue_attr: array of Rx queue attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * @tx_queue_attr: array of Tx queue attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * @cscn_mem: pointer to memory region containing the congestion SCN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *	it's size is larger than to accommodate alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * @cscn_mem_aligned: pointer to congestion SCN; it is computed as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *	PTR_ALIGN(cscn_mem, DPAA2_CSCN_ALIGN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * @cscn_dma: dma address used by the QMAN to write CSCN messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * @dev: device associated with the DPSECI object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * @mc_io: pointer to MC portal's I/O object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * @domain: IOMMU domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * @ppriv: per CPU pointers to privata data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct dpaa2_caam_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int dpsec_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u16 major_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u16 minor_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct dpseci_attr dpseci_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct dpseci_sec_attr sec_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct dpseci_rx_queue_attr rx_queue_attr[DPSECI_MAX_QUEUE_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct dpseci_tx_queue_attr tx_queue_attr[DPSECI_MAX_QUEUE_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	int num_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/* congestion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	void *cscn_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	void *cscn_mem_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	dma_addr_t cscn_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct fsl_mc_io *mc_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct iommu_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct dpaa2_caam_priv_per_cpu __percpu *ppriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct dentry *dfs_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * dpaa2_caam_priv_per_cpu - per CPU private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * @napi: napi structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * @net_dev: netdev used by napi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * @req_fqid: (virtual) request (Tx / enqueue) FQID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * @rsp_fqid: (virtual) response (Rx / dequeue) FQID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * @prio: internal queue number - index for dpaa2_caam_priv.*_queue_attr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * @nctx: notification context of response FQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * @store: where dequeued frames are stored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * @priv: backpointer to dpaa2_caam_priv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * @dpio: portal used for data path operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) struct dpaa2_caam_priv_per_cpu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct net_device net_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	int req_fqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	int rsp_fqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	int prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct dpaa2_io_notification_ctx nctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct dpaa2_io_store *store;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct dpaa2_caam_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct dpaa2_io *dpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* Length of a single buffer in the QI driver memory cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CAAM_QI_MEMCACHE_SIZE	512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  * aead_edesc - s/w-extended aead descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)  * @src_nents: number of segments in input scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * @dst_nents: number of segments in output scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * @iv_dma: dma address of iv for checking continuity and link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * @qm_sg_bytes: length of dma mapped h/w link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  * @qm_sg_dma: bus physical mapped address of h/w link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  * @assoclen: associated data length, in CAAM endianness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)  * @assoclen_dma: bus physical mapped address of req->assoclen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)  * @sgt: the h/w link table, followed by IV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct aead_edesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	int src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	int dst_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	dma_addr_t iv_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	dma_addr_t qm_sg_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	unsigned int assoclen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	dma_addr_t assoclen_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct dpaa2_sg_entry sgt[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * skcipher_edesc - s/w-extended skcipher descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * @src_nents: number of segments in input scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * @dst_nents: number of segments in output scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * @iv_dma: dma address of iv for checking continuity and link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  * @qm_sg_bytes: length of dma mapped qm_sg space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * @qm_sg_dma: I/O virtual address of h/w link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * @sgt: the h/w link table, followed by IV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct skcipher_edesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	int src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	int dst_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	dma_addr_t iv_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	int qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	dma_addr_t qm_sg_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct dpaa2_sg_entry sgt[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  * ahash_edesc - s/w-extended ahash descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  * @qm_sg_dma: I/O virtual address of h/w link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * @src_nents: number of segments in input scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * @qm_sg_bytes: length of dma mapped qm_sg space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * @sgt: pointer to h/w link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct ahash_edesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	dma_addr_t qm_sg_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	int src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	int qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct dpaa2_sg_entry sgt[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * caam_flc - Flow Context (FLC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * @flc: Flow Context options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  * @sh_desc: Shared Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct caam_flc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	u32 flc[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u32 sh_desc[MAX_SDLEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) } ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) enum optype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	ENCRYPT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	DECRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	NUM_OP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * caam_request - the request structure the driver application should fill while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  *                submitting a job to driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  * @fd_flt: Frame list table defining input and output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  *          fd_flt[0] - FLE pointing to output buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  *          fd_flt[1] - FLE pointing to input buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  * @fd_flt_dma: DMA address for the frame list table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  * @flc: Flow Context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  * @flc_dma: I/O virtual address of Flow Context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  * @cbk: Callback function to invoke when job is completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  * @ctx: arbit context attached with request by the application
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  * @edesc: extended descriptor; points to one of {skcipher,aead}_edesc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct caam_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct dpaa2_fl_entry fd_flt[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	dma_addr_t fd_flt_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	struct caam_flc *flc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	dma_addr_t flc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	void (*cbk)(void *ctx, u32 err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	void *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	void *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct skcipher_request fallback_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * dpaa2_caam_enqueue() - enqueue a crypto request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  * @dev: device associated with the DPSECI object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  * @req: pointer to caam_request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #endif	/* _CAAMALG_QI2_H_ */