^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2015-2016 Freescale Semiconductor Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2017-2019 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include "compat.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "caamalg_qi2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "dpseci_cmd.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "desc_constr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "error.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "sg_sw_sec4.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "sg_sw_qm2.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "key_gen.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "caamalg_desc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "caamhash_desc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "dpseci-debugfs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/fsl/mc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <soc/fsl/dpaa2-io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <soc/fsl/dpaa2-fd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <crypto/xts.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CAAM_CRA_PRIORITY 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* max key is sum of AES_MAX_KEY_SIZE, max split key size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CAAM_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) SHA512_DIGEST_SIZE * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * This is a a cache of buffers, from which the users of CAAM QI driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * can allocate short buffers. It's speedier than doing kmalloc on the hotpath.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * NOTE: A more elegant solution would be to have some headroom in the frames
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * being processed. This can be added by the dpaa2-eth driver. This would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * pose a problem for userspace application processing which cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * know of this limitation. So for now, this will work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * NOTE: The memcache is SMP-safe. No need to handle spinlocks in-here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct kmem_cache *qi_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct caam_alg_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int class1_alg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int class2_alg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) bool rfc3686;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) bool geniv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) bool nodkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct caam_aead_alg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct aead_alg aead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct caam_alg_entry caam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) bool registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct caam_skcipher_alg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct skcipher_alg skcipher;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct caam_alg_entry caam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) bool registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * struct caam_ctx - per-session context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @flc: Flow Contexts array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @key: [authentication key], encryption key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @flc_dma: I/O virtual addresses of the Flow Contexts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @key_dma: I/O virtual address of the key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @dir: DMA direction for mapping key and Flow Contexts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @dev: dpseci device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @adata: authentication algorithm details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @cdata: encryption algorithm details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @authsize: authentication tag (a.k.a. ICV / MAC) size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct caam_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct caam_flc flc[NUM_OP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 key[CAAM_MAX_KEY_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) dma_addr_t flc_dma[NUM_OP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) dma_addr_t key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum dma_data_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct alginfo adata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct alginfo cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) bool xts_key_fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct crypto_skcipher *fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void *dpaa2_caam_iova_to_virt(struct dpaa2_caam_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dma_addr_t iova_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) phys_addr_t phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) phys_addr = priv->domain ? iommu_iova_to_phys(priv->domain, iova_addr) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) iova_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return phys_to_virt(phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * qi_cache_zalloc - Allocate buffers from CAAM-QI cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Allocate data on the hotpath. Instead of using kzalloc, one can use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * services of the CAAM QI memory cache (backed by kmem_cache). The buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * will have a size of CAAM_QI_MEMCACHE_SIZE, which should be sufficient for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * hosting 16 SG entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @flags - flags that would be used for the equivalent kmalloc(..) call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Returns a pointer to a retrieved buffer on success or NULL on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static inline void *qi_cache_zalloc(gfp_t flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return kmem_cache_zalloc(qi_cache, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * qi_cache_free - Frees buffers allocated from CAAM-QI cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @obj - buffer previously allocated by qi_cache_zalloc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * No checking is being done, the call is a passthrough call to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * kmem_cache_free(...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline void qi_cache_free(void *obj)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) kmem_cache_free(qi_cache, obj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct caam_request *to_caam_req(struct crypto_async_request *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) switch (crypto_tfm_alg_type(areq->tfm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case CRYPTO_ALG_TYPE_SKCIPHER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return skcipher_request_ctx(skcipher_request_cast(areq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case CRYPTO_ALG_TYPE_AEAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return aead_request_ctx(container_of(areq, struct aead_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case CRYPTO_ALG_TYPE_AHASH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return ahash_request_ctx(ahash_request_cast(areq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void caam_unmap(struct device *dev, struct scatterlist *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct scatterlist *dst, int src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int dst_nents, dma_addr_t iv_dma, int ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) enum dma_data_direction iv_dir, dma_addr_t qm_sg_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int qm_sg_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (dst != src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (src_nents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (dst_nents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (iv_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dma_unmap_single(dev, iv_dma, ivsize, iv_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (qm_sg_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dma_unmap_single(dev, qm_sg_dma, qm_sg_bytes, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int aead_set_sh_desc(struct crypto_aead *aead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) typeof(*alg), aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned int ivsize = crypto_aead_ivsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct dpaa2_caam_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct caam_flc *flc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 ctx1_iv_off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 *nonce = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int data_len[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 inl_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) OP_ALG_AAI_CTR_MOD128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) const bool is_rfc3686 = alg->caam.rfc3686;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!ctx->cdata.keylen || !ctx->authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * AES-CTR needs to load IV in CONTEXT1 reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * at an offset of 128bits (16bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * CONTEXT1[255:128] = IV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (ctr_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ctx1_iv_off = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * RFC3686 specific:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * CONTEXT1[255:128] = {NONCE, IV, COUNTER}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (is_rfc3686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) nonce = (u32 *)((void *)ctx->key + ctx->adata.keylen_pad +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ctx->cdata.keylen - CTR_RFC3686_NONCE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * In case |user key| > |derived key|, using DKP<imm,imm> would result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * in invalid opcodes (last bytes of user key) in the resulting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * descriptor. Use DKP<ptr,imm> instead => both virtual and dma key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * addresses are needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ctx->adata.key_virt = ctx->key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ctx->adata.key_dma = ctx->key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) data_len[0] = ctx->adata.keylen_pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) data_len[1] = ctx->cdata.keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* aead_encrypt shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (desc_inline_query((alg->caam.geniv ? DESC_QI_AEAD_GIVENC_LEN :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) DESC_QI_AEAD_ENC_LEN) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) DESC_JOB_IO_LEN, data_len, &inl_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ARRAY_SIZE(data_len)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ctx->adata.key_inline = !!(inl_mask & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ctx->cdata.key_inline = !!(inl_mask & 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) flc = &ctx->flc[ENCRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (alg->caam.geniv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) cnstr_shdsc_aead_givencap(desc, &ctx->cdata, &ctx->adata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ivsize, ctx->authsize, is_rfc3686,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) nonce, ctx1_iv_off, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) priv->sec_attr.era);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ivsize, ctx->authsize, is_rfc3686, nonce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ctx1_iv_off, true, priv->sec_attr.era);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) sizeof(flc->flc) + desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* aead_decrypt shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (desc_inline_query(DESC_QI_AEAD_DEC_LEN +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) DESC_JOB_IO_LEN, data_len, &inl_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ARRAY_SIZE(data_len)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ctx->adata.key_inline = !!(inl_mask & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ctx->cdata.key_inline = !!(inl_mask & 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) flc = &ctx->flc[DECRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) cnstr_shdsc_aead_decap(desc, &ctx->cdata, &ctx->adata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ivsize, ctx->authsize, alg->caam.geniv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) is_rfc3686, nonce, ctx1_iv_off, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) priv->sec_attr.era);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sizeof(flc->flc) + desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int aead_setauthsize(struct crypto_aead *authenc, unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct caam_ctx *ctx = crypto_aead_ctx(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ctx->authsize = authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) aead_set_sh_desc(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int aead_setkey(struct crypto_aead *aead, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct crypto_authenc_keys keys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) goto badkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_dbg(dev, "keylen %d enckeylen %d authkeylen %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) keys.authkeylen + keys.enckeylen, keys.enckeylen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) keys.authkeylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) print_hex_dump_debug("key in @" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ctx->adata.keylen = keys.authkeylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) OP_ALG_ALGSEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) goto badkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) memcpy(ctx->key, keys.authkey, keys.authkeylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dma_sync_single_for_device(dev, ctx->key_dma, ctx->adata.keylen_pad +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) keys.enckeylen, ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) print_hex_dump_debug("ctx.key@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ctx->adata.keylen_pad + keys.enckeylen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ctx->cdata.keylen = keys.enckeylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) memzero_explicit(&keys, sizeof(keys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return aead_set_sh_desc(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) badkey:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) memzero_explicit(&keys, sizeof(keys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int des3_aead_setkey(struct crypto_aead *aead, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct crypto_authenc_keys keys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) err = crypto_authenc_extractkeys(&keys, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (unlikely(err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (keys.enckeylen != DES3_EDE_KEY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) err = crypto_des3_ede_verify_key(crypto_aead_tfm(aead), keys.enckey) ?:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) aead_setkey(aead, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) memzero_explicit(&keys, sizeof(keys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) bool encrypt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct crypto_aead *aead = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct caam_request *req_ctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) typeof(*alg), aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) GFP_KERNEL : GFP_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int src_len, dst_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct aead_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dma_addr_t qm_sg_dma, iv_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int ivsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned int authsize = ctx->authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int qm_sg_index = 0, qm_sg_nents = 0, qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int in_len, out_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct dpaa2_sg_entry *sg_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* allocate space for base edesc, link tables and IV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) edesc = qi_cache_zalloc(GFP_DMA | flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (unlikely(!edesc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev_err(dev, "could not allocate extended descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (unlikely(req->dst != req->src)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) src_len = req->assoclen + req->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dst_len = src_len + (encrypt ? authsize : (-authsize));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) src_nents = sg_nents_for_len(req->src, src_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (unlikely(src_nents < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_err(dev, "Insufficient bytes (%d) in src S/G\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) src_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return ERR_PTR(src_nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dst_nents = sg_nents_for_len(req->dst, dst_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (unlikely(dst_nents < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_err(dev, "Insufficient bytes (%d) in dst S/G\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dst_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return ERR_PTR(dst_nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (src_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mapped_src_nents = dma_map_sg(dev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (unlikely(!mapped_src_nents)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_err(dev, "unable to map source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) mapped_src_nents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (dst_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mapped_dst_nents = dma_map_sg(dev, req->dst, dst_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (unlikely(!mapped_dst_nents)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_err(dev, "unable to map destination\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dma_unmap_sg(dev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) mapped_dst_nents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) src_len = req->assoclen + req->cryptlen +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) (encrypt ? authsize : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) src_nents = sg_nents_for_len(req->src, src_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (unlikely(src_nents < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_err(dev, "Insufficient bytes (%d) in src S/G\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) src_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return ERR_PTR(src_nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mapped_src_nents = dma_map_sg(dev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (unlikely(!mapped_src_nents)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_err(dev, "unable to map source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if ((alg->caam.rfc3686 && encrypt) || !alg->caam.geniv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ivsize = crypto_aead_ivsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * Create S/G table: req->assoclen, [IV,] req->src [, req->dst].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * Input is not contiguous.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * HW reads 4 S/G entries at a time; make sure the reads don't go beyond
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * the end of the table by allocating more S/G entries. Logic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * if (src != dst && output S/G)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * pad output S/G, if needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * else if (src == dst && S/G)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * overlapping S/Gs; pad one of them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * else if (input S/G) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * pad input S/G, if needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) qm_sg_nents = 1 + !!ivsize + mapped_src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (mapped_dst_nents > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) qm_sg_nents += pad_sg_nents(mapped_dst_nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) else if ((req->src == req->dst) && (mapped_src_nents > 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) qm_sg_nents = max(pad_sg_nents(qm_sg_nents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 1 + !!ivsize +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pad_sg_nents(mapped_src_nents));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) qm_sg_nents = pad_sg_nents(qm_sg_nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sg_table = &edesc->sgt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) qm_sg_bytes = qm_sg_nents * sizeof(*sg_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (unlikely(offsetof(struct aead_edesc, sgt) + qm_sg_bytes + ivsize >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) CAAM_QI_MEMCACHE_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_err(dev, "No space for %d S/G entries and/or %dB IV\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) qm_sg_nents, ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) caam_unmap(dev, req->src, req->dst, src_nents, dst_nents, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 0, DMA_NONE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (ivsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u8 *iv = (u8 *)(sg_table + qm_sg_nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Make sure IV is located in a DMAable area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) memcpy(iv, req->iv, ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (dma_mapping_error(dev, iv_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dev_err(dev, "unable to map IV\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) caam_unmap(dev, req->src, req->dst, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dst_nents, 0, 0, DMA_NONE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) edesc->src_nents = src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) edesc->dst_nents = dst_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) edesc->iv_dma = iv_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if ((alg->caam.class1_alg_type & OP_ALG_ALGSEL_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) OP_ALG_ALGSEL_CHACHA20 && ivsize != CHACHAPOLY_IV_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * The associated data comes already with the IV but we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * to skip it when we authenticate or encrypt...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) edesc->assoclen = cpu_to_caam32(req->assoclen - ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) edesc->assoclen = cpu_to_caam32(req->assoclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) edesc->assoclen_dma = dma_map_single(dev, &edesc->assoclen, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (dma_mapping_error(dev, edesc->assoclen_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dev_err(dev, "unable to map assoclen\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) caam_unmap(dev, req->src, req->dst, src_nents, dst_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) iv_dma, ivsize, DMA_TO_DEVICE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dma_to_qm_sg_one(sg_table, edesc->assoclen_dma, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) qm_sg_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (ivsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dma_to_qm_sg_one(sg_table + qm_sg_index, iv_dma, ivsize, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) qm_sg_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) sg_to_qm_sg_last(req->src, src_len, sg_table + qm_sg_index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) qm_sg_index += mapped_src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (mapped_dst_nents > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) sg_to_qm_sg_last(req->dst, dst_len, sg_table + qm_sg_index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) qm_sg_dma = dma_map_single(dev, sg_table, qm_sg_bytes, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (dma_mapping_error(dev, qm_sg_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev_err(dev, "unable to map S/G table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dma_unmap_single(dev, edesc->assoclen_dma, 4, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) caam_unmap(dev, req->src, req->dst, src_nents, dst_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) iv_dma, ivsize, DMA_TO_DEVICE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) edesc->qm_sg_dma = qm_sg_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) edesc->qm_sg_bytes = qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) out_len = req->assoclen + req->cryptlen +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) (encrypt ? ctx->authsize : (-ctx->authsize));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) in_len = 4 + ivsize + req->assoclen + req->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dpaa2_fl_set_final(in_fle, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dpaa2_fl_set_addr(in_fle, qm_sg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dpaa2_fl_set_len(in_fle, in_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (req->dst == req->src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (mapped_src_nents == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) dpaa2_fl_set_addr(out_fle, sg_dma_address(req->src));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dpaa2_fl_set_format(out_fle, dpaa2_fl_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dpaa2_fl_set_addr(out_fle, qm_sg_dma +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) (1 + !!ivsize) * sizeof(*sg_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) } else if (!mapped_dst_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * crypto engine requires the output entry to be present when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * "frame list" FD is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * Since engine does not support FMT=2'b11 (unused entry type),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * leaving out_fle zeroized is the best option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) goto skip_out_fle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) } else if (mapped_dst_nents == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dpaa2_fl_set_addr(out_fle, sg_dma_address(req->dst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dpaa2_fl_set_format(out_fle, dpaa2_fl_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dpaa2_fl_set_addr(out_fle, qm_sg_dma + qm_sg_index *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) sizeof(*sg_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dpaa2_fl_set_len(out_fle, out_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) skip_out_fle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int chachapoly_set_sh_desc(struct crypto_aead *aead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned int ivsize = crypto_aead_ivsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct caam_flc *flc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u32 *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!ctx->cdata.keylen || !ctx->authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) flc = &ctx->flc[ENCRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) cnstr_shdsc_chachapoly(desc, &ctx->cdata, &ctx->adata, ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ctx->authsize, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) sizeof(flc->flc) + desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) flc = &ctx->flc[DECRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) cnstr_shdsc_chachapoly(desc, &ctx->cdata, &ctx->adata, ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ctx->authsize, false, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) sizeof(flc->flc) + desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int chachapoly_setauthsize(struct crypto_aead *aead,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (authsize != POLY1305_DIGEST_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ctx->authsize = authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return chachapoly_set_sh_desc(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int chachapoly_setkey(struct crypto_aead *aead, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unsigned int ivsize = crypto_aead_ivsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned int saltlen = CHACHAPOLY_IV_SIZE - ivsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (keylen != CHACHA_KEY_SIZE + saltlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ctx->cdata.key_virt = key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ctx->cdata.keylen = keylen - saltlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return chachapoly_set_sh_desc(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int gcm_set_sh_desc(struct crypto_aead *aead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) unsigned int ivsize = crypto_aead_ivsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct caam_flc *flc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ctx->cdata.keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (!ctx->cdata.keylen || !ctx->authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * AES GCM encrypt shared descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * Job Descriptor and Shared Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * must fit into the 64-word Descriptor h/w Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (rem_bytes >= DESC_QI_GCM_ENC_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ctx->cdata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ctx->cdata.key_virt = ctx->key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ctx->cdata.key_inline = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ctx->cdata.key_dma = ctx->key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) flc = &ctx->flc[ENCRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) cnstr_shdsc_gcm_encap(desc, &ctx->cdata, ivsize, ctx->authsize, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) sizeof(flc->flc) + desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * Job Descriptor and Shared Descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * must all fit into the 64-word Descriptor h/w Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (rem_bytes >= DESC_QI_GCM_DEC_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ctx->cdata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ctx->cdata.key_virt = ctx->key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ctx->cdata.key_inline = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ctx->cdata.key_dma = ctx->key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) flc = &ctx->flc[DECRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) cnstr_shdsc_gcm_decap(desc, &ctx->cdata, ivsize, ctx->authsize, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) sizeof(flc->flc) + desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int gcm_setauthsize(struct crypto_aead *authenc, unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct caam_ctx *ctx = crypto_aead_ctx(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) err = crypto_gcm_check_authsize(authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ctx->authsize = authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) gcm_set_sh_desc(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int gcm_setkey(struct crypto_aead *aead,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret = aes_check_keylen(keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) print_hex_dump_debug("key in @" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) memcpy(ctx->key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dma_sync_single_for_device(dev, ctx->key_dma, keylen, ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ctx->cdata.keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return gcm_set_sh_desc(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static int rfc4106_set_sh_desc(struct crypto_aead *aead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) unsigned int ivsize = crypto_aead_ivsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct caam_flc *flc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u32 *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ctx->cdata.keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (!ctx->cdata.keylen || !ctx->authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ctx->cdata.key_virt = ctx->key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * RFC4106 encrypt shared descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * Job Descriptor and Shared Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * must fit into the 64-word Descriptor h/w Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (rem_bytes >= DESC_QI_RFC4106_ENC_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ctx->cdata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ctx->cdata.key_inline = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ctx->cdata.key_dma = ctx->key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) flc = &ctx->flc[ENCRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) cnstr_shdsc_rfc4106_encap(desc, &ctx->cdata, ivsize, ctx->authsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) sizeof(flc->flc) + desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * Job Descriptor and Shared Descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * must all fit into the 64-word Descriptor h/w Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (rem_bytes >= DESC_QI_RFC4106_DEC_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ctx->cdata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ctx->cdata.key_inline = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ctx->cdata.key_dma = ctx->key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) flc = &ctx->flc[DECRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) cnstr_shdsc_rfc4106_decap(desc, &ctx->cdata, ivsize, ctx->authsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) sizeof(flc->flc) + desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int rfc4106_setauthsize(struct crypto_aead *authenc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct caam_ctx *ctx = crypto_aead_ctx(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) err = crypto_rfc4106_check_authsize(authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ctx->authsize = authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) rfc4106_set_sh_desc(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static int rfc4106_setkey(struct crypto_aead *aead,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ret = aes_check_keylen(keylen - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) print_hex_dump_debug("key in @" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) memcpy(ctx->key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * The last four bytes of the key material are used as the salt value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * in the nonce. Update the AES key length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ctx->cdata.keylen = keylen - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dma_sync_single_for_device(dev, ctx->key_dma, ctx->cdata.keylen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return rfc4106_set_sh_desc(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int rfc4543_set_sh_desc(struct crypto_aead *aead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) unsigned int ivsize = crypto_aead_ivsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) struct caam_flc *flc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u32 *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ctx->cdata.keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (!ctx->cdata.keylen || !ctx->authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ctx->cdata.key_virt = ctx->key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * RFC4543 encrypt shared descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * Job Descriptor and Shared Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * must fit into the 64-word Descriptor h/w Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (rem_bytes >= DESC_QI_RFC4543_ENC_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ctx->cdata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ctx->cdata.key_inline = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ctx->cdata.key_dma = ctx->key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) flc = &ctx->flc[ENCRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) cnstr_shdsc_rfc4543_encap(desc, &ctx->cdata, ivsize, ctx->authsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) sizeof(flc->flc) + desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * Job Descriptor and Shared Descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * must all fit into the 64-word Descriptor h/w Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (rem_bytes >= DESC_QI_RFC4543_DEC_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ctx->cdata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ctx->cdata.key_inline = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ctx->cdata.key_dma = ctx->key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) flc = &ctx->flc[DECRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) cnstr_shdsc_rfc4543_decap(desc, &ctx->cdata, ivsize, ctx->authsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) sizeof(flc->flc) + desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int rfc4543_setauthsize(struct crypto_aead *authenc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct caam_ctx *ctx = crypto_aead_ctx(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (authsize != 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) ctx->authsize = authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) rfc4543_set_sh_desc(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int rfc4543_setkey(struct crypto_aead *aead,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ret = aes_check_keylen(keylen - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) print_hex_dump_debug("key in @" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) memcpy(ctx->key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * The last four bytes of the key material are used as the salt value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * in the nonce. Update the AES key length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ctx->cdata.keylen = keylen - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) dma_sync_single_for_device(dev, ctx->key_dma, ctx->cdata.keylen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return rfc4543_set_sh_desc(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static int skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) unsigned int keylen, const u32 ctx1_iv_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct caam_skcipher_alg *alg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) container_of(crypto_skcipher_alg(skcipher),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct caam_skcipher_alg, skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct caam_flc *flc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) unsigned int ivsize = crypto_skcipher_ivsize(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) u32 *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) const bool is_rfc3686 = alg->caam.rfc3686;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) print_hex_dump_debug("key in @" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ctx->cdata.keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ctx->cdata.key_virt = key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ctx->cdata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* skcipher_encrypt shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) flc = &ctx->flc[ENCRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) cnstr_shdsc_skcipher_encap(desc, &ctx->cdata, ivsize, is_rfc3686,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) ctx1_iv_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) sizeof(flc->flc) + desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /* skcipher_decrypt shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) flc = &ctx->flc[DECRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) cnstr_shdsc_skcipher_decap(desc, &ctx->cdata, ivsize, is_rfc3686,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ctx1_iv_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) sizeof(flc->flc) + desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static int aes_skcipher_setkey(struct crypto_skcipher *skcipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) err = aes_check_keylen(keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return skcipher_setkey(skcipher, key, keylen, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static int rfc3686_skcipher_setkey(struct crypto_skcipher *skcipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) u32 ctx1_iv_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * RFC3686 specific:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * | CONTEXT1[255:128] = {NONCE, IV, COUNTER}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * | *key = {KEY, NONCE}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) keylen -= CTR_RFC3686_NONCE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) err = aes_check_keylen(keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return skcipher_setkey(skcipher, key, keylen, ctx1_iv_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static int ctr_skcipher_setkey(struct crypto_skcipher *skcipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) u32 ctx1_iv_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * AES-CTR needs to load IV in CONTEXT1 reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * at an offset of 128bits (16bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * CONTEXT1[255:128] = IV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ctx1_iv_off = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) err = aes_check_keylen(keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return skcipher_setkey(skcipher, key, keylen, ctx1_iv_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static int chacha20_skcipher_setkey(struct crypto_skcipher *skcipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (keylen != CHACHA_KEY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return skcipher_setkey(skcipher, key, keylen, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static int des_skcipher_setkey(struct crypto_skcipher *skcipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return verify_skcipher_des_key(skcipher, key) ?:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) skcipher_setkey(skcipher, key, keylen, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static int des3_skcipher_setkey(struct crypto_skcipher *skcipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return verify_skcipher_des3_key(skcipher, key) ?:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) skcipher_setkey(skcipher, key, keylen, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static int xts_skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct dpaa2_caam_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct caam_flc *flc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) u32 *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) err = xts_verify_key(skcipher, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) dev_dbg(dev, "key size mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (keylen != 2 * AES_KEYSIZE_128 && keylen != 2 * AES_KEYSIZE_256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ctx->xts_key_fallback = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (priv->sec_attr.era <= 8 || ctx->xts_key_fallback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) err = crypto_skcipher_setkey(ctx->fallback, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ctx->cdata.keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ctx->cdata.key_virt = key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ctx->cdata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /* xts_skcipher_encrypt shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) flc = &ctx->flc[ENCRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) cnstr_shdsc_xts_skcipher_encap(desc, &ctx->cdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) dma_sync_single_for_device(dev, ctx->flc_dma[ENCRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) sizeof(flc->flc) + desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /* xts_skcipher_decrypt shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) flc = &ctx->flc[DECRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) cnstr_shdsc_xts_skcipher_decap(desc, &ctx->cdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) dma_sync_single_for_device(dev, ctx->flc_dma[DECRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) sizeof(flc->flc) + desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static struct skcipher_edesc *skcipher_edesc_alloc(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct caam_request *req_ctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) GFP_KERNEL : GFP_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct skcipher_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dma_addr_t iv_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) u8 *iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) int ivsize = crypto_skcipher_ivsize(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) int dst_sg_idx, qm_sg_ents, qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct dpaa2_sg_entry *sg_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) src_nents = sg_nents_for_len(req->src, req->cryptlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (unlikely(src_nents < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) dev_err(dev, "Insufficient bytes (%d) in src S/G\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) req->cryptlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return ERR_PTR(src_nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (unlikely(req->dst != req->src)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) dst_nents = sg_nents_for_len(req->dst, req->cryptlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (unlikely(dst_nents < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) dev_err(dev, "Insufficient bytes (%d) in dst S/G\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) req->cryptlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return ERR_PTR(dst_nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) mapped_src_nents = dma_map_sg(dev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (unlikely(!mapped_src_nents)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dev_err(dev, "unable to map source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) mapped_dst_nents = dma_map_sg(dev, req->dst, dst_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (unlikely(!mapped_dst_nents)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) dev_err(dev, "unable to map destination\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) dma_unmap_sg(dev, req->src, src_nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) mapped_src_nents = dma_map_sg(dev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (unlikely(!mapped_src_nents)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) dev_err(dev, "unable to map source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) qm_sg_ents = 1 + mapped_src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) dst_sg_idx = qm_sg_ents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * Input, output HW S/G tables: [IV, src][dst, IV]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * IV entries point to the same buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * If src == dst, S/G entries are reused (S/G tables overlap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * HW reads 4 S/G entries at a time; make sure the reads don't go beyond
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) * the end of the table by allocating more S/G entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (req->src != req->dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) qm_sg_ents += pad_sg_nents(mapped_dst_nents + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) qm_sg_ents = 1 + pad_sg_nents(qm_sg_ents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) qm_sg_bytes = qm_sg_ents * sizeof(struct dpaa2_sg_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (unlikely(offsetof(struct skcipher_edesc, sgt) + qm_sg_bytes +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ivsize > CAAM_QI_MEMCACHE_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) dev_err(dev, "No space for %d S/G entries and/or %dB IV\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) qm_sg_ents, ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) caam_unmap(dev, req->src, req->dst, src_nents, dst_nents, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) 0, DMA_NONE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /* allocate space for base edesc, link tables and IV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) edesc = qi_cache_zalloc(GFP_DMA | flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (unlikely(!edesc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) dev_err(dev, "could not allocate extended descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) caam_unmap(dev, req->src, req->dst, src_nents, dst_nents, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) 0, DMA_NONE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /* Make sure IV is located in a DMAable area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) sg_table = &edesc->sgt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) iv = (u8 *)(sg_table + qm_sg_ents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) memcpy(iv, req->iv, ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) iv_dma = dma_map_single(dev, iv, ivsize, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (dma_mapping_error(dev, iv_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) dev_err(dev, "unable to map IV\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) caam_unmap(dev, req->src, req->dst, src_nents, dst_nents, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) 0, DMA_NONE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) edesc->src_nents = src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) edesc->dst_nents = dst_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) edesc->iv_dma = iv_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) edesc->qm_sg_bytes = qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) dma_to_qm_sg_one(sg_table, iv_dma, ivsize, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) sg_to_qm_sg(req->src, req->cryptlen, sg_table + 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (req->src != req->dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) sg_to_qm_sg(req->dst, req->cryptlen, sg_table + dst_sg_idx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) dma_to_qm_sg_one(sg_table + dst_sg_idx + mapped_dst_nents, iv_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ivsize, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) edesc->qm_sg_dma = dma_map_single(dev, sg_table, edesc->qm_sg_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (dma_mapping_error(dev, edesc->qm_sg_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) dev_err(dev, "unable to map S/G table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) caam_unmap(dev, req->src, req->dst, src_nents, dst_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) iv_dma, ivsize, DMA_BIDIRECTIONAL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) dpaa2_fl_set_final(in_fle, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) dpaa2_fl_set_len(in_fle, req->cryptlen + ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) dpaa2_fl_set_len(out_fle, req->cryptlen + ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) dpaa2_fl_set_format(out_fle, dpaa2_fl_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (req->src == req->dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) dpaa2_fl_set_addr(out_fle, edesc->qm_sg_dma +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) sizeof(*sg_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) dpaa2_fl_set_addr(out_fle, edesc->qm_sg_dma + dst_sg_idx *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) sizeof(*sg_table));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static void aead_unmap(struct device *dev, struct aead_edesc *edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct crypto_aead *aead = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) int ivsize = crypto_aead_ivsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) caam_unmap(dev, req->src, req->dst, edesc->src_nents, edesc->dst_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) edesc->iv_dma, ivsize, DMA_TO_DEVICE, edesc->qm_sg_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) edesc->qm_sg_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) dma_unmap_single(dev, edesc->assoclen_dma, 4, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static void skcipher_unmap(struct device *dev, struct skcipher_edesc *edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) int ivsize = crypto_skcipher_ivsize(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) caam_unmap(dev, req->src, req->dst, edesc->src_nents, edesc->dst_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) edesc->iv_dma, ivsize, DMA_BIDIRECTIONAL, edesc->qm_sg_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) edesc->qm_sg_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static void aead_encrypt_done(void *cbk_ctx, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct crypto_async_request *areq = cbk_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct aead_request *req = container_of(areq, struct aead_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) struct caam_request *req_ctx = to_caam_req(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct aead_edesc *edesc = req_ctx->edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) struct crypto_aead *aead = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) int ecode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) dev_dbg(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (unlikely(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) ecode = caam_qi2_strstatus(ctx->dev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) aead_unmap(ctx->dev, edesc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) aead_request_complete(req, ecode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static void aead_decrypt_done(void *cbk_ctx, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct crypto_async_request *areq = cbk_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct aead_request *req = container_of(areq, struct aead_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct caam_request *req_ctx = to_caam_req(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct aead_edesc *edesc = req_ctx->edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct crypto_aead *aead = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) int ecode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) dev_dbg(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (unlikely(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) ecode = caam_qi2_strstatus(ctx->dev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) aead_unmap(ctx->dev, edesc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) aead_request_complete(req, ecode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static int aead_encrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) struct aead_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct crypto_aead *aead = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) struct caam_request *caam_req = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) /* allocate extended descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) edesc = aead_edesc_alloc(req, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (IS_ERR(edesc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) return PTR_ERR(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) caam_req->flc = &ctx->flc[ENCRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) caam_req->flc_dma = ctx->flc_dma[ENCRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) caam_req->cbk = aead_encrypt_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) caam_req->ctx = &req->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) caam_req->edesc = edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (ret != -EINPROGRESS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) aead_unmap(ctx->dev, edesc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static int aead_decrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) struct aead_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) struct crypto_aead *aead = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) struct caam_request *caam_req = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /* allocate extended descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) edesc = aead_edesc_alloc(req, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (IS_ERR(edesc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return PTR_ERR(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) caam_req->flc = &ctx->flc[DECRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) caam_req->flc_dma = ctx->flc_dma[DECRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) caam_req->cbk = aead_decrypt_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) caam_req->ctx = &req->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) caam_req->edesc = edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (ret != -EINPROGRESS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) aead_unmap(ctx->dev, edesc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) static int ipsec_gcm_encrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return crypto_ipsec_check_assoclen(req->assoclen) ? : aead_encrypt(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static int ipsec_gcm_decrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return crypto_ipsec_check_assoclen(req->assoclen) ? : aead_decrypt(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static void skcipher_encrypt_done(void *cbk_ctx, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) struct crypto_async_request *areq = cbk_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) struct skcipher_request *req = skcipher_request_cast(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) struct caam_request *req_ctx = to_caam_req(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct skcipher_edesc *edesc = req_ctx->edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) int ecode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) int ivsize = crypto_skcipher_ivsize(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) dev_dbg(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (unlikely(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) ecode = caam_qi2_strstatus(ctx->dev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) print_hex_dump_debug("dstiv @" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) edesc->src_nents > 1 ? 100 : ivsize, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) caam_dump_sg("dst @" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) DUMP_PREFIX_ADDRESS, 16, 4, req->dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) edesc->dst_nents > 1 ? 100 : req->cryptlen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) skcipher_unmap(ctx->dev, edesc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) * The crypto API expects us to set the IV (req->iv) to the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) * ciphertext block (CBC mode) or last counter (CTR mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) * This is used e.g. by the CTS mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (!ecode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) memcpy(req->iv, (u8 *)&edesc->sgt[0] + edesc->qm_sg_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) skcipher_request_complete(req, ecode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) static void skcipher_decrypt_done(void *cbk_ctx, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) struct crypto_async_request *areq = cbk_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) struct skcipher_request *req = skcipher_request_cast(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) struct caam_request *req_ctx = to_caam_req(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) struct skcipher_edesc *edesc = req_ctx->edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) int ecode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) int ivsize = crypto_skcipher_ivsize(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) dev_dbg(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (unlikely(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) ecode = caam_qi2_strstatus(ctx->dev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) print_hex_dump_debug("dstiv @" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) edesc->src_nents > 1 ? 100 : ivsize, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) caam_dump_sg("dst @" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) DUMP_PREFIX_ADDRESS, 16, 4, req->dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) edesc->dst_nents > 1 ? 100 : req->cryptlen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) skcipher_unmap(ctx->dev, edesc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) * The crypto API expects us to set the IV (req->iv) to the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * ciphertext block (CBC mode) or last counter (CTR mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * This is used e.g. by the CTS mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (!ecode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) memcpy(req->iv, (u8 *)&edesc->sgt[0] + edesc->qm_sg_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) skcipher_request_complete(req, ecode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static inline bool xts_skcipher_ivsize(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) unsigned int ivsize = crypto_skcipher_ivsize(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) return !!get_unaligned((u64 *)(req->iv + (ivsize / 2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static int skcipher_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) struct skcipher_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct caam_request *caam_req = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) struct dpaa2_caam_priv *priv = dev_get_drvdata(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) * XTS is expected to return an error even for input length = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) * Note that the case input length < block size will be caught during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) * HW offloading and return an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (!req->cryptlen && !ctx->fallback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) if (ctx->fallback && ((priv->sec_attr.era <= 8 && xts_skcipher_ivsize(req)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) ctx->xts_key_fallback)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) skcipher_request_set_tfm(&caam_req->fallback_req, ctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) skcipher_request_set_callback(&caam_req->fallback_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) req->base.flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) req->base.complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) req->base.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) skcipher_request_set_crypt(&caam_req->fallback_req, req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) req->dst, req->cryptlen, req->iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return crypto_skcipher_encrypt(&caam_req->fallback_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) /* allocate extended descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) edesc = skcipher_edesc_alloc(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (IS_ERR(edesc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) return PTR_ERR(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) caam_req->flc = &ctx->flc[ENCRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) caam_req->flc_dma = ctx->flc_dma[ENCRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) caam_req->cbk = skcipher_encrypt_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) caam_req->ctx = &req->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) caam_req->edesc = edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) if (ret != -EINPROGRESS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) skcipher_unmap(ctx->dev, edesc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static int skcipher_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) struct skcipher_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct caam_request *caam_req = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct dpaa2_caam_priv *priv = dev_get_drvdata(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * XTS is expected to return an error even for input length = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) * Note that the case input length < block size will be caught during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) * HW offloading and return an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (!req->cryptlen && !ctx->fallback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (ctx->fallback && ((priv->sec_attr.era <= 8 && xts_skcipher_ivsize(req)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) ctx->xts_key_fallback)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) skcipher_request_set_tfm(&caam_req->fallback_req, ctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) skcipher_request_set_callback(&caam_req->fallback_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) req->base.flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) req->base.complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) req->base.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) skcipher_request_set_crypt(&caam_req->fallback_req, req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) req->dst, req->cryptlen, req->iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) return crypto_skcipher_decrypt(&caam_req->fallback_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /* allocate extended descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) edesc = skcipher_edesc_alloc(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) if (IS_ERR(edesc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) return PTR_ERR(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) caam_req->flc = &ctx->flc[DECRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) caam_req->flc_dma = ctx->flc_dma[DECRYPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) caam_req->cbk = skcipher_decrypt_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) caam_req->ctx = &req->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) caam_req->edesc = edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) ret = dpaa2_caam_enqueue(ctx->dev, caam_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) if (ret != -EINPROGRESS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) skcipher_unmap(ctx->dev, edesc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static int caam_cra_init(struct caam_ctx *ctx, struct caam_alg_entry *caam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) bool uses_dkp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /* copy descriptor header template value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) ctx->cdata.algtype = OP_TYPE_CLASS1_ALG | caam->class1_alg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam->class2_alg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) ctx->dev = caam->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) ctx->dir = uses_dkp ? DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) dma_addr = dma_map_single_attrs(ctx->dev, ctx->flc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) offsetof(struct caam_ctx, flc_dma),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) ctx->dir, DMA_ATTR_SKIP_CPU_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (dma_mapping_error(ctx->dev, dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) dev_err(ctx->dev, "unable to map key, shared descriptors\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) for (i = 0; i < NUM_OP; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) ctx->flc_dma[i] = dma_addr + i * sizeof(ctx->flc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) ctx->key_dma = dma_addr + NUM_OP * sizeof(ctx->flc[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) static int caam_cra_init_skcipher(struct crypto_skcipher *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) struct caam_skcipher_alg *caam_alg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) container_of(alg, typeof(*caam_alg), skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) struct caam_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) u32 alg_aai = caam_alg->caam.class1_alg_type & OP_ALG_AAI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (alg_aai == OP_ALG_AAI_XTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) const char *tfm_name = crypto_tfm_alg_name(&tfm->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) struct crypto_skcipher *fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) fallback = crypto_alloc_skcipher(tfm_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) CRYPTO_ALG_NEED_FALLBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) if (IS_ERR(fallback)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) dev_err(caam_alg->caam.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) "Failed to allocate %s fallback: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) tfm_name, PTR_ERR(fallback));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) return PTR_ERR(fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) ctx->fallback = fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) crypto_skcipher_set_reqsize(tfm, sizeof(struct caam_request) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) crypto_skcipher_reqsize(fallback));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) crypto_skcipher_set_reqsize(tfm, sizeof(struct caam_request));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) ret = caam_cra_init(ctx, &caam_alg->caam, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) if (ret && ctx->fallback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) crypto_free_skcipher(ctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) static int caam_cra_init_aead(struct crypto_aead *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) struct aead_alg *alg = crypto_aead_alg(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) struct caam_aead_alg *caam_alg = container_of(alg, typeof(*caam_alg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) crypto_aead_set_reqsize(tfm, sizeof(struct caam_request));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) return caam_cra_init(crypto_aead_ctx(tfm), &caam_alg->caam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) !caam_alg->caam.nodkp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static void caam_exit_common(struct caam_ctx *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) dma_unmap_single_attrs(ctx->dev, ctx->flc_dma[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) offsetof(struct caam_ctx, flc_dma), ctx->dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) DMA_ATTR_SKIP_CPU_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static void caam_cra_exit(struct crypto_skcipher *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) struct caam_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (ctx->fallback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) crypto_free_skcipher(ctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) caam_exit_common(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static void caam_cra_exit_aead(struct crypto_aead *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) caam_exit_common(crypto_aead_ctx(tfm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) static struct caam_skcipher_alg driver_algs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .cra_name = "cbc(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .cra_driver_name = "cbc-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .setkey = aes_skcipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .encrypt = skcipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .decrypt = skcipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .cra_name = "cbc(des3_ede)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .cra_driver_name = "cbc-3des-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .setkey = des3_skcipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .encrypt = skcipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .decrypt = skcipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .min_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .max_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .caam.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .cra_name = "cbc(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .cra_driver_name = "cbc-des-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .setkey = des_skcipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .encrypt = skcipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .decrypt = skcipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .min_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .max_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .caam.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .cra_name = "ctr(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .cra_driver_name = "ctr-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .setkey = ctr_skcipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .encrypt = skcipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .decrypt = skcipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .chunksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .caam.class1_alg_type = OP_ALG_ALGSEL_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) OP_ALG_AAI_CTR_MOD128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .cra_name = "rfc3686(ctr(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .cra_driver_name = "rfc3686-ctr-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .setkey = rfc3686_skcipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .encrypt = skcipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .decrypt = skcipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .min_keysize = AES_MIN_KEY_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) CTR_RFC3686_NONCE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .max_keysize = AES_MAX_KEY_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) CTR_RFC3686_NONCE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .chunksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) .class1_alg_type = OP_ALG_ALGSEL_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) OP_ALG_AAI_CTR_MOD128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .rfc3686 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .cra_name = "xts(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .cra_driver_name = "xts-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .cra_flags = CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .setkey = xts_skcipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .encrypt = skcipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .decrypt = skcipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .min_keysize = 2 * AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .max_keysize = 2 * AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_XTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .cra_name = "chacha20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .cra_driver_name = "chacha20-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .setkey = chacha20_skcipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .encrypt = skcipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .decrypt = skcipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .min_keysize = CHACHA_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .max_keysize = CHACHA_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .ivsize = CHACHA_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .caam.class1_alg_type = OP_ALG_ALGSEL_CHACHA20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) static struct caam_aead_alg driver_aeads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .cra_name = "rfc4106(gcm(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .cra_driver_name = "rfc4106-gcm-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .setkey = rfc4106_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .setauthsize = rfc4106_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .encrypt = ipsec_gcm_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .decrypt = ipsec_gcm_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .ivsize = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .nodkp = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .cra_name = "rfc4543(gcm(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .cra_driver_name = "rfc4543-gcm-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .setkey = rfc4543_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .setauthsize = rfc4543_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .encrypt = ipsec_gcm_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .decrypt = ipsec_gcm_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .ivsize = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .nodkp = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) /* Galois Counter Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .cra_name = "gcm(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .cra_driver_name = "gcm-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .setkey = gcm_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .setauthsize = gcm_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .ivsize = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .nodkp = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) /* single-pass ipsec_esp descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .cra_name = "authenc(hmac(md5),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .cra_driver_name = "authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) "cbc-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .class2_alg_type = OP_ALG_ALGSEL_MD5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .cra_name = "echainiv(authenc(hmac(md5),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) "cbc(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .cra_driver_name = "echainiv-authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) "cbc-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .class2_alg_type = OP_ALG_ALGSEL_MD5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .cra_name = "authenc(hmac(sha1),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .cra_driver_name = "authenc-hmac-sha1-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) "cbc-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .cra_name = "echainiv(authenc(hmac(sha1),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) "cbc(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) "hmac-sha1-cbc-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .cra_name = "authenc(hmac(sha224),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) .cra_driver_name = "authenc-hmac-sha224-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) "cbc-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .cra_name = "echainiv(authenc(hmac(sha224),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) "cbc(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) "hmac-sha224-cbc-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .cra_name = "authenc(hmac(sha256),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .cra_driver_name = "authenc-hmac-sha256-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) "cbc-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .cra_name = "echainiv(authenc(hmac(sha256),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) "cbc(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) "hmac-sha256-cbc-aes-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) "caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .cra_name = "authenc(hmac(sha384),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .cra_driver_name = "authenc-hmac-sha384-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) "cbc-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .maxauthsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .cra_name = "echainiv(authenc(hmac(sha384),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) "cbc(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) "hmac-sha384-cbc-aes-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) "caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .maxauthsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .cra_name = "authenc(hmac(sha512),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .cra_driver_name = "authenc-hmac-sha512-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) "cbc-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .maxauthsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .cra_name = "echainiv(authenc(hmac(sha512),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) "cbc(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) "hmac-sha512-cbc-aes-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) "caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .maxauthsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .cra_driver_name = "authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) "cbc-des3_ede-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .class2_alg_type = OP_ALG_ALGSEL_MD5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .cra_name = "echainiv(authenc(hmac(md5),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) "cbc(des3_ede)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .cra_driver_name = "echainiv-authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) "cbc-des3_ede-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .class2_alg_type = OP_ALG_ALGSEL_MD5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .cra_name = "authenc(hmac(sha1),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) .cra_driver_name = "authenc-hmac-sha1-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) "cbc-des3_ede-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .cra_name = "echainiv(authenc(hmac(sha1),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) "cbc(des3_ede)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) "hmac-sha1-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) "cbc-des3_ede-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .cra_name = "authenc(hmac(sha224),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .cra_driver_name = "authenc-hmac-sha224-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) "cbc-des3_ede-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .cra_name = "echainiv(authenc(hmac(sha224),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) "cbc(des3_ede)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) "hmac-sha224-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) "cbc-des3_ede-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .cra_name = "authenc(hmac(sha256),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .cra_driver_name = "authenc-hmac-sha256-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) "cbc-des3_ede-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .cra_name = "echainiv(authenc(hmac(sha256),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) "cbc(des3_ede)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) "hmac-sha256-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) "cbc-des3_ede-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .cra_name = "authenc(hmac(sha384),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .cra_driver_name = "authenc-hmac-sha384-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) "cbc-des3_ede-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .maxauthsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .cra_name = "echainiv(authenc(hmac(sha384),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) "cbc(des3_ede)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) "hmac-sha384-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) "cbc-des3_ede-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .maxauthsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) .cra_name = "authenc(hmac(sha512),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .cra_driver_name = "authenc-hmac-sha512-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) "cbc-des3_ede-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .maxauthsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) .cra_name = "echainiv(authenc(hmac(sha512),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) "cbc(des3_ede)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) "hmac-sha512-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) "cbc-des3_ede-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .maxauthsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .cra_name = "authenc(hmac(md5),cbc(des))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .cra_driver_name = "authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) "cbc-des-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .class2_alg_type = OP_ALG_ALGSEL_MD5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) .cra_name = "echainiv(authenc(hmac(md5),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) "cbc(des)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) .cra_driver_name = "echainiv-authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) "cbc-des-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .class2_alg_type = OP_ALG_ALGSEL_MD5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .cra_name = "authenc(hmac(sha1),cbc(des))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .cra_driver_name = "authenc-hmac-sha1-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) "cbc-des-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .cra_name = "echainiv(authenc(hmac(sha1),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) "cbc(des)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) "hmac-sha1-cbc-des-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) .cra_name = "authenc(hmac(sha224),cbc(des))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) .cra_driver_name = "authenc-hmac-sha224-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) "cbc-des-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .cra_name = "echainiv(authenc(hmac(sha224),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) "cbc(des)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) "hmac-sha224-cbc-des-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) "caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .cra_name = "authenc(hmac(sha256),cbc(des))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) .cra_driver_name = "authenc-hmac-sha256-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) "cbc-des-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) .cra_name = "echainiv(authenc(hmac(sha256),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) "cbc(des)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) "hmac-sha256-cbc-des-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) "caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .cra_name = "authenc(hmac(sha384),cbc(des))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) .cra_driver_name = "authenc-hmac-sha384-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) "cbc-des-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) .maxauthsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) .cra_name = "echainiv(authenc(hmac(sha384),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) "cbc(des)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) "hmac-sha384-cbc-des-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) "caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) .maxauthsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) .cra_name = "authenc(hmac(sha512),cbc(des))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) .cra_driver_name = "authenc-hmac-sha512-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) "cbc-des-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) .maxauthsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) .cra_name = "echainiv(authenc(hmac(sha512),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) "cbc(des)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) "hmac-sha512-cbc-des-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) "caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) .maxauthsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) .cra_name = "authenc(hmac(md5),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) "rfc3686(ctr(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) .cra_driver_name = "authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) "rfc3686-ctr-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) .class1_alg_type = OP_ALG_ALGSEL_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) OP_ALG_AAI_CTR_MOD128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) .class2_alg_type = OP_ALG_ALGSEL_MD5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) .rfc3686 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) .cra_name = "seqiv(authenc("
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) "hmac(md5),rfc3686(ctr(aes))))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) .cra_driver_name = "seqiv-authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) "rfc3686-ctr-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .class1_alg_type = OP_ALG_ALGSEL_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) OP_ALG_AAI_CTR_MOD128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .class2_alg_type = OP_ALG_ALGSEL_MD5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) .rfc3686 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) .cra_name = "authenc(hmac(sha1),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) "rfc3686(ctr(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) .cra_driver_name = "authenc-hmac-sha1-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) "rfc3686-ctr-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) .class1_alg_type = OP_ALG_ALGSEL_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) OP_ALG_AAI_CTR_MOD128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) .rfc3686 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .cra_name = "seqiv(authenc("
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) "hmac(sha1),rfc3686(ctr(aes))))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) .cra_driver_name = "seqiv-authenc-hmac-sha1-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) "rfc3686-ctr-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) .class1_alg_type = OP_ALG_ALGSEL_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) OP_ALG_AAI_CTR_MOD128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) .rfc3686 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) .cra_name = "authenc(hmac(sha224),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) "rfc3686(ctr(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) .cra_driver_name = "authenc-hmac-sha224-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) "rfc3686-ctr-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) .class1_alg_type = OP_ALG_ALGSEL_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) OP_ALG_AAI_CTR_MOD128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) .rfc3686 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) .cra_name = "seqiv(authenc("
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) "hmac(sha224),rfc3686(ctr(aes))))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) .cra_driver_name = "seqiv-authenc-hmac-sha224-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) "rfc3686-ctr-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) .class1_alg_type = OP_ALG_ALGSEL_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) OP_ALG_AAI_CTR_MOD128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) .rfc3686 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) .cra_name = "authenc(hmac(sha256),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) "rfc3686(ctr(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) .cra_driver_name = "authenc-hmac-sha256-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) "rfc3686-ctr-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) .class1_alg_type = OP_ALG_ALGSEL_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) OP_ALG_AAI_CTR_MOD128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) .rfc3686 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) .cra_name = "seqiv(authenc(hmac(sha256),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) "rfc3686(ctr(aes))))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) .cra_driver_name = "seqiv-authenc-hmac-sha256-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) "rfc3686-ctr-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) .class1_alg_type = OP_ALG_ALGSEL_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) OP_ALG_AAI_CTR_MOD128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) .rfc3686 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) .cra_name = "authenc(hmac(sha384),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) "rfc3686(ctr(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) .cra_driver_name = "authenc-hmac-sha384-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) "rfc3686-ctr-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) .maxauthsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) .class1_alg_type = OP_ALG_ALGSEL_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) OP_ALG_AAI_CTR_MOD128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) .rfc3686 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) .cra_name = "seqiv(authenc(hmac(sha384),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) "rfc3686(ctr(aes))))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) .cra_driver_name = "seqiv-authenc-hmac-sha384-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) "rfc3686-ctr-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) .maxauthsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) .class1_alg_type = OP_ALG_ALGSEL_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) OP_ALG_AAI_CTR_MOD128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) .rfc3686 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) .cra_name = "rfc7539(chacha20,poly1305)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) .cra_driver_name = "rfc7539-chacha20-poly1305-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) "caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) .setkey = chachapoly_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) .setauthsize = chachapoly_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) .ivsize = CHACHAPOLY_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) .maxauthsize = POLY1305_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) .class1_alg_type = OP_ALG_ALGSEL_CHACHA20 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) OP_ALG_AAI_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) .class2_alg_type = OP_ALG_ALGSEL_POLY1305 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) OP_ALG_AAI_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) .nodkp = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) .cra_name = "rfc7539esp(chacha20,poly1305)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) .cra_driver_name = "rfc7539esp-chacha20-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) "poly1305-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) .setkey = chachapoly_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) .setauthsize = chachapoly_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) .ivsize = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) .maxauthsize = POLY1305_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) .class1_alg_type = OP_ALG_ALGSEL_CHACHA20 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) OP_ALG_AAI_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) .class2_alg_type = OP_ALG_ALGSEL_POLY1305 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) OP_ALG_AAI_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) .nodkp = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) .cra_name = "authenc(hmac(sha512),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) "rfc3686(ctr(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) .cra_driver_name = "authenc-hmac-sha512-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) "rfc3686-ctr-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) .maxauthsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) .class1_alg_type = OP_ALG_ALGSEL_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) OP_ALG_AAI_CTR_MOD128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) .rfc3686 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) .cra_name = "seqiv(authenc(hmac(sha512),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) "rfc3686(ctr(aes))))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) .cra_driver_name = "seqiv-authenc-hmac-sha512-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) "rfc3686-ctr-aes-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) .maxauthsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) .class1_alg_type = OP_ALG_ALGSEL_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) OP_ALG_AAI_CTR_MOD128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) .rfc3686 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) static void caam_skcipher_alg_init(struct caam_skcipher_alg *t_alg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) struct skcipher_alg *alg = &t_alg->skcipher;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) alg->base.cra_module = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) alg->base.cra_priority = CAAM_CRA_PRIORITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) alg->base.cra_ctxsize = sizeof(struct caam_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) alg->base.cra_flags |= (CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) CRYPTO_ALG_KERN_DRIVER_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) alg->init = caam_cra_init_skcipher;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) alg->exit = caam_cra_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) static void caam_aead_alg_init(struct caam_aead_alg *t_alg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) struct aead_alg *alg = &t_alg->aead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) alg->base.cra_module = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) alg->base.cra_priority = CAAM_CRA_PRIORITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) alg->base.cra_ctxsize = sizeof(struct caam_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) CRYPTO_ALG_KERN_DRIVER_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) alg->init = caam_cra_init_aead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) alg->exit = caam_cra_exit_aead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) /* max hash key is max split key size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) #define CAAM_MAX_HASH_KEY_SIZE (SHA512_DIGEST_SIZE * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) #define CAAM_MAX_HASH_BLOCK_SIZE SHA512_BLOCK_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) /* caam context sizes for hashes: running digest + 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) #define HASH_MSG_LEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) #define MAX_CTX_LEN (HASH_MSG_LEN + SHA512_DIGEST_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) enum hash_optype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) UPDATE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) UPDATE_FIRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) FINALIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) DIGEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) HASH_NUM_OP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) * struct caam_hash_ctx - ahash per-session context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) * @flc: Flow Contexts array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) * @key: authentication key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) * @flc_dma: I/O virtual addresses of the Flow Contexts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) * @dev: dpseci device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) * @ctx_len: size of Context Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) * @adata: hashing algorithm details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) struct caam_hash_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) struct caam_flc flc[HASH_NUM_OP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) u8 key[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) dma_addr_t flc_dma[HASH_NUM_OP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) int ctx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) struct alginfo adata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) /* ahash state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) struct caam_hash_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) struct caam_request caam_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) dma_addr_t buf_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) dma_addr_t ctx_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) int ctx_dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) u8 buf[CAAM_MAX_HASH_BLOCK_SIZE] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) int buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) int next_buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) u8 caam_ctx[MAX_CTX_LEN] ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) int (*update)(struct ahash_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) int (*final)(struct ahash_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) int (*finup)(struct ahash_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) struct caam_export_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) u8 buf[CAAM_MAX_HASH_BLOCK_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) u8 caam_ctx[MAX_CTX_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) int buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) int (*update)(struct ahash_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) int (*final)(struct ahash_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) int (*finup)(struct ahash_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) /* Map current buffer in state (if length > 0) and put it in link table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) static inline int buf_map_to_qm_sg(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) struct dpaa2_sg_entry *qm_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) struct caam_hash_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) int buflen = state->buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) if (!buflen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) state->buf_dma = dma_map_single(dev, state->buf, buflen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) if (dma_mapping_error(dev, state->buf_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) dev_err(dev, "unable to map buf\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) state->buf_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) dma_to_qm_sg_one(qm_sg, state->buf_dma, buflen, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) /* Map state->caam_ctx, and add it to link table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) static inline int ctx_map_to_qm_sg(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) struct caam_hash_state *state, int ctx_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) struct dpaa2_sg_entry *qm_sg, u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) state->ctx_dma_len = ctx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) state->ctx_dma = dma_map_single(dev, state->caam_ctx, ctx_len, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) if (dma_mapping_error(dev, state->ctx_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) dev_err(dev, "unable to map ctx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) state->ctx_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) dma_to_qm_sg_one(qm_sg, state->ctx_dma, ctx_len, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) static int ahash_set_sh_desc(struct crypto_ahash *ahash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) int digestsize = crypto_ahash_digestsize(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) struct dpaa2_caam_priv *priv = dev_get_drvdata(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) struct caam_flc *flc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) u32 *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) /* ahash_update shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) flc = &ctx->flc[UPDATE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_UPDATE, ctx->ctx_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) ctx->ctx_len, true, priv->sec_attr.era);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) dma_sync_single_for_device(ctx->dev, ctx->flc_dma[UPDATE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) desc_bytes(desc), DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) print_hex_dump_debug("ahash update shdesc@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) /* ahash_update_first shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) flc = &ctx->flc[UPDATE_FIRST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_INIT, ctx->ctx_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) ctx->ctx_len, false, priv->sec_attr.era);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) dma_sync_single_for_device(ctx->dev, ctx->flc_dma[UPDATE_FIRST],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) desc_bytes(desc), DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) print_hex_dump_debug("ahash update first shdesc@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) /* ahash_final shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) flc = &ctx->flc[FINALIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_FINALIZE, digestsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) ctx->ctx_len, true, priv->sec_attr.era);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) dma_sync_single_for_device(ctx->dev, ctx->flc_dma[FINALIZE],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) desc_bytes(desc), DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) print_hex_dump_debug("ahash final shdesc@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) /* ahash_digest shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) flc = &ctx->flc[DIGEST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) cnstr_shdsc_ahash(desc, &ctx->adata, OP_ALG_AS_INITFINAL, digestsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) ctx->ctx_len, false, priv->sec_attr.era);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) dma_sync_single_for_device(ctx->dev, ctx->flc_dma[DIGEST],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) desc_bytes(desc), DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) print_hex_dump_debug("ahash digest shdesc@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) struct split_key_sh_result {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) static void split_key_sh_done(void *cbk_ctx, u32 err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) struct split_key_sh_result *res = cbk_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) dev_dbg(res->dev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) res->err = err ? caam_qi2_strstatus(res->dev, err) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) complete(&res->completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) /* Digest hash size if it is too large */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) static int hash_digest_key(struct caam_hash_ctx *ctx, u32 *keylen, u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) u32 digestsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) struct caam_request *req_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) u32 *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) struct split_key_sh_result result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) dma_addr_t key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) struct caam_flc *flc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) dma_addr_t flc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) int ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) struct dpaa2_fl_entry *in_fle, *out_fle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) req_ctx = kzalloc(sizeof(*req_ctx), GFP_KERNEL | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) if (!req_ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) in_fle = &req_ctx->fd_flt[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) out_fle = &req_ctx->fd_flt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) flc = kzalloc(sizeof(*flc), GFP_KERNEL | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) if (!flc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) goto err_flc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) key_dma = dma_map_single(ctx->dev, key, *keylen, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) if (dma_mapping_error(ctx->dev, key_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) dev_err(ctx->dev, "unable to map key memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) goto err_key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) desc = flc->sh_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) init_sh_desc(desc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) /* descriptor to perform unkeyed hash on key_in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) append_operation(desc, ctx->adata.algtype | OP_ALG_ENCRYPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) OP_ALG_AS_INITFINAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) append_seq_fifo_load(desc, *keylen, FIFOLD_CLASS_CLASS2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_MSG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) append_seq_store(desc, digestsize, LDST_CLASS_2_CCB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) LDST_SRCDST_BYTE_CONTEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) flc->flc[1] = cpu_to_caam32(desc_len(desc)); /* SDL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) flc_dma = dma_map_single(ctx->dev, flc, sizeof(flc->flc) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) desc_bytes(desc), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) if (dma_mapping_error(ctx->dev, flc_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) dev_err(ctx->dev, "unable to map shared descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) goto err_flc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) dpaa2_fl_set_final(in_fle, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) dpaa2_fl_set_format(in_fle, dpaa2_fl_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) dpaa2_fl_set_addr(in_fle, key_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) dpaa2_fl_set_len(in_fle, *keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) dpaa2_fl_set_addr(out_fle, key_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) dpaa2_fl_set_len(out_fle, digestsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) print_hex_dump_debug("key_in@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) DUMP_PREFIX_ADDRESS, 16, 4, key, *keylen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) print_hex_dump_debug("shdesc@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) result.err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) init_completion(&result.completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) result.dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) req_ctx->flc = flc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) req_ctx->flc_dma = flc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) req_ctx->cbk = split_key_sh_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) req_ctx->ctx = &result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) if (ret == -EINPROGRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) /* in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) wait_for_completion(&result.completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) ret = result.err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) print_hex_dump_debug("digested key@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) DUMP_PREFIX_ADDRESS, 16, 4, key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) digestsize, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) dma_unmap_single(ctx->dev, flc_dma, sizeof(flc->flc) + desc_bytes(desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) err_flc_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) dma_unmap_single(ctx->dev, key_dma, *keylen, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) err_key_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) kfree(flc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) err_flc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) kfree(req_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) *keylen = digestsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) static int ahash_setkey(struct crypto_ahash *ahash, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) unsigned int blocksize = crypto_tfm_alg_blocksize(&ahash->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) unsigned int digestsize = crypto_ahash_digestsize(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) u8 *hashed_key = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) dev_dbg(ctx->dev, "keylen %d blocksize %d\n", keylen, blocksize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) if (keylen > blocksize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) hashed_key = kmemdup(key, keylen, GFP_KERNEL | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) if (!hashed_key)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) ret = hash_digest_key(ctx, &keylen, hashed_key, digestsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) goto bad_free_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) key = hashed_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) ctx->adata.keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) OP_ALG_ALGSEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) if (ctx->adata.keylen_pad > CAAM_MAX_HASH_KEY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) goto bad_free_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) ctx->adata.key_virt = key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) ctx->adata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) * In case |user key| > |derived key|, using DKP<imm,imm> would result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) * in invalid opcodes (last bytes of user key) in the resulting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) * descriptor. Use DKP<ptr,imm> instead => both virtual and dma key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) * addresses are needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) if (keylen > ctx->adata.keylen_pad) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) memcpy(ctx->key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) dma_sync_single_for_device(ctx->dev, ctx->adata.key_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) ctx->adata.keylen_pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) ret = ahash_set_sh_desc(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) kfree(hashed_key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) bad_free_key:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) kfree(hashed_key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) static inline void ahash_unmap(struct device *dev, struct ahash_edesc *edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) if (edesc->src_nents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) dma_unmap_sg(dev, req->src, edesc->src_nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) if (edesc->qm_sg_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) dma_unmap_single(dev, edesc->qm_sg_dma, edesc->qm_sg_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) if (state->buf_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) dma_unmap_single(dev, state->buf_dma, state->buflen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) state->buf_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) static inline void ahash_unmap_ctx(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) struct ahash_edesc *edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) struct ahash_request *req, u32 flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) if (state->ctx_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) dma_unmap_single(dev, state->ctx_dma, state->ctx_dma_len, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) state->ctx_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) ahash_unmap(dev, edesc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) static void ahash_done(void *cbk_ctx, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) struct crypto_async_request *areq = cbk_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) struct ahash_request *req = ahash_request_cast(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) struct ahash_edesc *edesc = state->caam_req.edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) int digestsize = crypto_ahash_digestsize(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) int ecode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) dev_dbg(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) if (unlikely(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) ecode = caam_qi2_strstatus(ctx->dev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) ahash_unmap_ctx(ctx->dev, edesc, req, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) memcpy(req->result, state->caam_ctx, digestsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) print_hex_dump_debug("ctx@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) ctx->ctx_len, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) req->base.complete(&req->base, ecode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) static void ahash_done_bi(void *cbk_ctx, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) struct crypto_async_request *areq = cbk_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) struct ahash_request *req = ahash_request_cast(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) struct ahash_edesc *edesc = state->caam_req.edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) int ecode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) dev_dbg(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) if (unlikely(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) ecode = caam_qi2_strstatus(ctx->dev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) ahash_unmap_ctx(ctx->dev, edesc, req, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) scatterwalk_map_and_copy(state->buf, req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) req->nbytes - state->next_buflen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) state->next_buflen, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) state->buflen = state->next_buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) print_hex_dump_debug("buf@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) DUMP_PREFIX_ADDRESS, 16, 4, state->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) state->buflen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) print_hex_dump_debug("ctx@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) ctx->ctx_len, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) if (req->result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) print_hex_dump_debug("result@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) DUMP_PREFIX_ADDRESS, 16, 4, req->result,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) crypto_ahash_digestsize(ahash), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) req->base.complete(&req->base, ecode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) static void ahash_done_ctx_src(void *cbk_ctx, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) struct crypto_async_request *areq = cbk_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) struct ahash_request *req = ahash_request_cast(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) struct ahash_edesc *edesc = state->caam_req.edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) int digestsize = crypto_ahash_digestsize(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) int ecode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) dev_dbg(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) if (unlikely(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) ecode = caam_qi2_strstatus(ctx->dev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) ahash_unmap_ctx(ctx->dev, edesc, req, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) memcpy(req->result, state->caam_ctx, digestsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) print_hex_dump_debug("ctx@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) ctx->ctx_len, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) req->base.complete(&req->base, ecode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) static void ahash_done_ctx_dst(void *cbk_ctx, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) struct crypto_async_request *areq = cbk_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) struct ahash_request *req = ahash_request_cast(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) struct ahash_edesc *edesc = state->caam_req.edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) int ecode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) dev_dbg(ctx->dev, "%s %d: err 0x%x\n", __func__, __LINE__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) if (unlikely(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) ecode = caam_qi2_strstatus(ctx->dev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) ahash_unmap_ctx(ctx->dev, edesc, req, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) scatterwalk_map_and_copy(state->buf, req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) req->nbytes - state->next_buflen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) state->next_buflen, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) state->buflen = state->next_buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) print_hex_dump_debug("buf@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) DUMP_PREFIX_ADDRESS, 16, 4, state->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) state->buflen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) print_hex_dump_debug("ctx@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) ctx->ctx_len, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) if (req->result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) print_hex_dump_debug("result@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) DUMP_PREFIX_ADDRESS, 16, 4, req->result,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) crypto_ahash_digestsize(ahash), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) req->base.complete(&req->base, ecode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) static int ahash_update_ctx(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) struct caam_request *req_ctx = &state->caam_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) GFP_KERNEL : GFP_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) u8 *buf = state->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) int *buflen = &state->buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) int *next_buflen = &state->next_buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) int in_len = *buflen + req->nbytes, to_hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) int src_nents, mapped_nents, qm_sg_bytes, qm_sg_src_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) struct ahash_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) *next_buflen = in_len & (crypto_tfm_alg_blocksize(&ahash->base) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) to_hash = in_len - *next_buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) if (to_hash) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) struct dpaa2_sg_entry *sg_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) int src_len = req->nbytes - *next_buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) src_nents = sg_nents_for_len(req->src, src_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) if (src_nents < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) dev_err(ctx->dev, "Invalid number of src SG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) return src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) if (src_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) if (!mapped_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) dev_err(ctx->dev, "unable to DMA map source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) mapped_nents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) /* allocate space for base edesc and link tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) edesc = qi_cache_zalloc(GFP_DMA | flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) if (!edesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) dma_unmap_sg(ctx->dev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) edesc->src_nents = src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) qm_sg_src_index = 1 + (*buflen ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) qm_sg_bytes = pad_sg_nents(qm_sg_src_index + mapped_nents) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) sizeof(*sg_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) sg_table = &edesc->sgt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) ret = ctx_map_to_qm_sg(ctx->dev, state, ctx->ctx_len, sg_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) ret = buf_map_to_qm_sg(ctx->dev, sg_table + 1, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) if (mapped_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) sg_to_qm_sg_last(req->src, src_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) sg_table + qm_sg_src_index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) dpaa2_sg_set_final(sg_table + qm_sg_src_index - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) qm_sg_bytes, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) dev_err(ctx->dev, "unable to map S/G table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) edesc->qm_sg_bytes = qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) dpaa2_fl_set_final(in_fle, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) dpaa2_fl_set_len(in_fle, ctx->ctx_len + to_hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) dpaa2_fl_set_addr(out_fle, state->ctx_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) dpaa2_fl_set_len(out_fle, ctx->ctx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) req_ctx->flc = &ctx->flc[UPDATE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) req_ctx->flc_dma = ctx->flc_dma[UPDATE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) req_ctx->cbk = ahash_done_bi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) req_ctx->ctx = &req->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) req_ctx->edesc = edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) if (ret != -EINPROGRESS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) !(ret == -EBUSY &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) } else if (*next_buflen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) scatterwalk_map_and_copy(buf + *buflen, req->src, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) req->nbytes, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) *buflen = *next_buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) print_hex_dump_debug("buf@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) DUMP_PREFIX_ADDRESS, 16, 4, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) *buflen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) unmap_ctx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) ahash_unmap_ctx(ctx->dev, edesc, req, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) static int ahash_final_ctx(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) struct caam_request *req_ctx = &state->caam_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) GFP_KERNEL : GFP_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) int buflen = state->buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) int qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) int digestsize = crypto_ahash_digestsize(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) struct ahash_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) struct dpaa2_sg_entry *sg_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) /* allocate space for base edesc and link tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) edesc = qi_cache_zalloc(GFP_DMA | flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) if (!edesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) qm_sg_bytes = pad_sg_nents(1 + (buflen ? 1 : 0)) * sizeof(*sg_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) sg_table = &edesc->sgt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) ret = ctx_map_to_qm_sg(ctx->dev, state, ctx->ctx_len, sg_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) ret = buf_map_to_qm_sg(ctx->dev, sg_table + 1, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) dpaa2_sg_set_final(sg_table + (buflen ? 1 : 0), true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table, qm_sg_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) dev_err(ctx->dev, "unable to map S/G table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) edesc->qm_sg_bytes = qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) dpaa2_fl_set_final(in_fle, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) dpaa2_fl_set_len(in_fle, ctx->ctx_len + buflen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) dpaa2_fl_set_addr(out_fle, state->ctx_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) dpaa2_fl_set_len(out_fle, digestsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) req_ctx->flc = &ctx->flc[FINALIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) req_ctx->flc_dma = ctx->flc_dma[FINALIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) req_ctx->cbk = ahash_done_ctx_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) req_ctx->ctx = &req->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) req_ctx->edesc = edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) if (ret == -EINPROGRESS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) unmap_ctx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) ahash_unmap_ctx(ctx->dev, edesc, req, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) static int ahash_finup_ctx(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) struct caam_request *req_ctx = &state->caam_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) GFP_KERNEL : GFP_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) int buflen = state->buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) int qm_sg_bytes, qm_sg_src_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) int src_nents, mapped_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) int digestsize = crypto_ahash_digestsize(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) struct ahash_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) struct dpaa2_sg_entry *sg_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) src_nents = sg_nents_for_len(req->src, req->nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) if (src_nents < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) dev_err(ctx->dev, "Invalid number of src SG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) return src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) if (src_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) if (!mapped_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) dev_err(ctx->dev, "unable to DMA map source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) mapped_nents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) /* allocate space for base edesc and link tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) edesc = qi_cache_zalloc(GFP_DMA | flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) if (!edesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) dma_unmap_sg(ctx->dev, req->src, src_nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) edesc->src_nents = src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) qm_sg_src_index = 1 + (buflen ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) qm_sg_bytes = pad_sg_nents(qm_sg_src_index + mapped_nents) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) sizeof(*sg_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) sg_table = &edesc->sgt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) ret = ctx_map_to_qm_sg(ctx->dev, state, ctx->ctx_len, sg_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) ret = buf_map_to_qm_sg(ctx->dev, sg_table + 1, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) sg_to_qm_sg_last(req->src, req->nbytes, sg_table + qm_sg_src_index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table, qm_sg_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) dev_err(ctx->dev, "unable to map S/G table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) edesc->qm_sg_bytes = qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) dpaa2_fl_set_final(in_fle, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) dpaa2_fl_set_len(in_fle, ctx->ctx_len + buflen + req->nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) dpaa2_fl_set_addr(out_fle, state->ctx_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) dpaa2_fl_set_len(out_fle, digestsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) req_ctx->flc = &ctx->flc[FINALIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) req_ctx->flc_dma = ctx->flc_dma[FINALIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) req_ctx->cbk = ahash_done_ctx_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) req_ctx->ctx = &req->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) req_ctx->edesc = edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) if (ret == -EINPROGRESS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) unmap_ctx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) ahash_unmap_ctx(ctx->dev, edesc, req, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) static int ahash_digest(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) struct caam_request *req_ctx = &state->caam_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) GFP_KERNEL : GFP_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) int digestsize = crypto_ahash_digestsize(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) int src_nents, mapped_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) struct ahash_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) int ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) state->buf_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) src_nents = sg_nents_for_len(req->src, req->nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) if (src_nents < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) dev_err(ctx->dev, "Invalid number of src SG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) return src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) if (src_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) if (!mapped_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) dev_err(ctx->dev, "unable to map source for DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) mapped_nents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) /* allocate space for base edesc and link tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) edesc = qi_cache_zalloc(GFP_DMA | flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) if (!edesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) dma_unmap_sg(ctx->dev, req->src, src_nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) edesc->src_nents = src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) if (mapped_nents > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) int qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) struct dpaa2_sg_entry *sg_table = &edesc->sgt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) qm_sg_bytes = pad_sg_nents(mapped_nents) * sizeof(*sg_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) sg_to_qm_sg_last(req->src, req->nbytes, sg_table, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) qm_sg_bytes, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) dev_err(ctx->dev, "unable to map S/G table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) edesc->qm_sg_bytes = qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) dpaa2_fl_set_format(in_fle, dpaa2_fl_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) dpaa2_fl_set_addr(in_fle, sg_dma_address(req->src));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) state->ctx_dma_len = digestsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) state->ctx_dma = dma_map_single(ctx->dev, state->caam_ctx, digestsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) if (dma_mapping_error(ctx->dev, state->ctx_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) dev_err(ctx->dev, "unable to map ctx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) state->ctx_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) dpaa2_fl_set_final(in_fle, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) dpaa2_fl_set_len(in_fle, req->nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) dpaa2_fl_set_addr(out_fle, state->ctx_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) dpaa2_fl_set_len(out_fle, digestsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) req_ctx->flc = &ctx->flc[DIGEST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) req_ctx->flc_dma = ctx->flc_dma[DIGEST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) req_ctx->cbk = ahash_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) req_ctx->ctx = &req->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) req_ctx->edesc = edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) if (ret == -EINPROGRESS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) ahash_unmap_ctx(ctx->dev, edesc, req, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) static int ahash_final_no_ctx(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) struct caam_request *req_ctx = &state->caam_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) GFP_KERNEL : GFP_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) u8 *buf = state->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) int buflen = state->buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) int digestsize = crypto_ahash_digestsize(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) struct ahash_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) int ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) /* allocate space for base edesc and link tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) edesc = qi_cache_zalloc(GFP_DMA | flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) if (!edesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) if (buflen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) state->buf_dma = dma_map_single(ctx->dev, buf, buflen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) if (dma_mapping_error(ctx->dev, state->buf_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) dev_err(ctx->dev, "unable to map src\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) state->ctx_dma_len = digestsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) state->ctx_dma = dma_map_single(ctx->dev, state->caam_ctx, digestsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) if (dma_mapping_error(ctx->dev, state->ctx_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) dev_err(ctx->dev, "unable to map ctx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) state->ctx_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) dpaa2_fl_set_final(in_fle, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) * crypto engine requires the input entry to be present when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) * "frame list" FD is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) * Since engine does not support FMT=2'b11 (unused entry type), leaving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) * in_fle zeroized (except for "Final" flag) is the best option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) if (buflen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) dpaa2_fl_set_format(in_fle, dpaa2_fl_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) dpaa2_fl_set_addr(in_fle, state->buf_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) dpaa2_fl_set_len(in_fle, buflen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) dpaa2_fl_set_addr(out_fle, state->ctx_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) dpaa2_fl_set_len(out_fle, digestsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) req_ctx->flc = &ctx->flc[DIGEST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) req_ctx->flc_dma = ctx->flc_dma[DIGEST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) req_ctx->cbk = ahash_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) req_ctx->ctx = &req->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) req_ctx->edesc = edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) if (ret == -EINPROGRESS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) (ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) ahash_unmap_ctx(ctx->dev, edesc, req, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) static int ahash_update_no_ctx(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) struct caam_request *req_ctx = &state->caam_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) GFP_KERNEL : GFP_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) u8 *buf = state->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) int *buflen = &state->buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) int *next_buflen = &state->next_buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) int in_len = *buflen + req->nbytes, to_hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) int qm_sg_bytes, src_nents, mapped_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) struct ahash_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) *next_buflen = in_len & (crypto_tfm_alg_blocksize(&ahash->base) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) to_hash = in_len - *next_buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) if (to_hash) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) struct dpaa2_sg_entry *sg_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) int src_len = req->nbytes - *next_buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) src_nents = sg_nents_for_len(req->src, src_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) if (src_nents < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) dev_err(ctx->dev, "Invalid number of src SG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) return src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) if (src_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) if (!mapped_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) dev_err(ctx->dev, "unable to DMA map source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) mapped_nents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) /* allocate space for base edesc and link tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) edesc = qi_cache_zalloc(GFP_DMA | flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) if (!edesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) dma_unmap_sg(ctx->dev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) edesc->src_nents = src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) qm_sg_bytes = pad_sg_nents(1 + mapped_nents) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) sizeof(*sg_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) sg_table = &edesc->sgt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) ret = buf_map_to_qm_sg(ctx->dev, sg_table, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) sg_to_qm_sg_last(req->src, src_len, sg_table + 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) qm_sg_bytes, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) dev_err(ctx->dev, "unable to map S/G table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) edesc->qm_sg_bytes = qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) state->ctx_dma_len = ctx->ctx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) state->ctx_dma = dma_map_single(ctx->dev, state->caam_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) ctx->ctx_len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) if (dma_mapping_error(ctx->dev, state->ctx_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) dev_err(ctx->dev, "unable to map ctx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) state->ctx_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) dpaa2_fl_set_final(in_fle, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) dpaa2_fl_set_len(in_fle, to_hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) dpaa2_fl_set_addr(out_fle, state->ctx_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) dpaa2_fl_set_len(out_fle, ctx->ctx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) req_ctx->flc = &ctx->flc[UPDATE_FIRST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) req_ctx->flc_dma = ctx->flc_dma[UPDATE_FIRST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) req_ctx->cbk = ahash_done_ctx_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) req_ctx->ctx = &req->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) req_ctx->edesc = edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) if (ret != -EINPROGRESS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) !(ret == -EBUSY &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) state->update = ahash_update_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) state->finup = ahash_finup_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) state->final = ahash_final_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) } else if (*next_buflen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) scatterwalk_map_and_copy(buf + *buflen, req->src, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) req->nbytes, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) *buflen = *next_buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) print_hex_dump_debug("buf@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) DUMP_PREFIX_ADDRESS, 16, 4, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) *buflen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) unmap_ctx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) ahash_unmap_ctx(ctx->dev, edesc, req, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) static int ahash_finup_no_ctx(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) struct caam_request *req_ctx = &state->caam_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) GFP_KERNEL : GFP_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) int buflen = state->buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) int qm_sg_bytes, src_nents, mapped_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) int digestsize = crypto_ahash_digestsize(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) struct ahash_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) struct dpaa2_sg_entry *sg_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) int ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) src_nents = sg_nents_for_len(req->src, req->nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) if (src_nents < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) dev_err(ctx->dev, "Invalid number of src SG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) return src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) if (src_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) if (!mapped_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) dev_err(ctx->dev, "unable to DMA map source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) mapped_nents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) /* allocate space for base edesc and link tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) edesc = qi_cache_zalloc(GFP_DMA | flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) if (!edesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) dma_unmap_sg(ctx->dev, req->src, src_nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) edesc->src_nents = src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) qm_sg_bytes = pad_sg_nents(2 + mapped_nents) * sizeof(*sg_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) sg_table = &edesc->sgt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) ret = buf_map_to_qm_sg(ctx->dev, sg_table, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) sg_to_qm_sg_last(req->src, req->nbytes, sg_table + 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table, qm_sg_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) dev_err(ctx->dev, "unable to map S/G table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) edesc->qm_sg_bytes = qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) state->ctx_dma_len = digestsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) state->ctx_dma = dma_map_single(ctx->dev, state->caam_ctx, digestsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) if (dma_mapping_error(ctx->dev, state->ctx_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) dev_err(ctx->dev, "unable to map ctx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) state->ctx_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) dpaa2_fl_set_final(in_fle, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) dpaa2_fl_set_len(in_fle, buflen + req->nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) dpaa2_fl_set_addr(out_fle, state->ctx_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) dpaa2_fl_set_len(out_fle, digestsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) req_ctx->flc = &ctx->flc[DIGEST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) req_ctx->flc_dma = ctx->flc_dma[DIGEST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) req_ctx->cbk = ahash_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) req_ctx->ctx = &req->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) req_ctx->edesc = edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) if (ret != -EINPROGRESS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) !(ret == -EBUSY && req->base.flags & CRYPTO_TFM_REQ_MAY_BACKLOG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) goto unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) ahash_unmap_ctx(ctx->dev, edesc, req, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) static int ahash_update_first(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) struct crypto_ahash *ahash = crypto_ahash_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) struct caam_request *req_ctx = &state->caam_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) struct dpaa2_fl_entry *in_fle = &req_ctx->fd_flt[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) struct dpaa2_fl_entry *out_fle = &req_ctx->fd_flt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) GFP_KERNEL : GFP_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) u8 *buf = state->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) int *buflen = &state->buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) int *next_buflen = &state->next_buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) int to_hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) int src_nents, mapped_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) struct ahash_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) *next_buflen = req->nbytes & (crypto_tfm_alg_blocksize(&ahash->base) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) to_hash = req->nbytes - *next_buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) if (to_hash) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) struct dpaa2_sg_entry *sg_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) int src_len = req->nbytes - *next_buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) src_nents = sg_nents_for_len(req->src, src_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) if (src_nents < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) dev_err(ctx->dev, "Invalid number of src SG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) return src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) if (src_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) mapped_nents = dma_map_sg(ctx->dev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) if (!mapped_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) dev_err(ctx->dev, "unable to map source for DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) mapped_nents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) /* allocate space for base edesc and link tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) edesc = qi_cache_zalloc(GFP_DMA | flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) if (!edesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) dma_unmap_sg(ctx->dev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) edesc->src_nents = src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) sg_table = &edesc->sgt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) memset(&req_ctx->fd_flt, 0, sizeof(req_ctx->fd_flt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) dpaa2_fl_set_final(in_fle, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) dpaa2_fl_set_len(in_fle, to_hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) if (mapped_nents > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) int qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) sg_to_qm_sg_last(req->src, src_len, sg_table, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) qm_sg_bytes = pad_sg_nents(mapped_nents) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) sizeof(*sg_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) edesc->qm_sg_dma = dma_map_single(ctx->dev, sg_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) qm_sg_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) if (dma_mapping_error(ctx->dev, edesc->qm_sg_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) dev_err(ctx->dev, "unable to map S/G table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) edesc->qm_sg_bytes = qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) dpaa2_fl_set_format(in_fle, dpaa2_fl_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) dpaa2_fl_set_addr(in_fle, edesc->qm_sg_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) dpaa2_fl_set_format(in_fle, dpaa2_fl_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) dpaa2_fl_set_addr(in_fle, sg_dma_address(req->src));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) state->ctx_dma_len = ctx->ctx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) state->ctx_dma = dma_map_single(ctx->dev, state->caam_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) ctx->ctx_len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) if (dma_mapping_error(ctx->dev, state->ctx_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) dev_err(ctx->dev, "unable to map ctx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) state->ctx_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) dpaa2_fl_set_format(out_fle, dpaa2_fl_single);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) dpaa2_fl_set_addr(out_fle, state->ctx_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) dpaa2_fl_set_len(out_fle, ctx->ctx_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) req_ctx->flc = &ctx->flc[UPDATE_FIRST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) req_ctx->flc_dma = ctx->flc_dma[UPDATE_FIRST];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) req_ctx->cbk = ahash_done_ctx_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) req_ctx->ctx = &req->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) req_ctx->edesc = edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) ret = dpaa2_caam_enqueue(ctx->dev, req_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) if (ret != -EINPROGRESS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) !(ret == -EBUSY && req->base.flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) CRYPTO_TFM_REQ_MAY_BACKLOG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) goto unmap_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) state->update = ahash_update_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) state->finup = ahash_finup_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) state->final = ahash_final_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) } else if (*next_buflen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) state->update = ahash_update_no_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) state->finup = ahash_finup_no_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) state->final = ahash_final_no_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) scatterwalk_map_and_copy(buf, req->src, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) req->nbytes, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) *buflen = *next_buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) print_hex_dump_debug("buf@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) DUMP_PREFIX_ADDRESS, 16, 4, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) *buflen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) unmap_ctx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) ahash_unmap_ctx(ctx->dev, edesc, req, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) static int ahash_finup_first(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) return ahash_digest(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) static int ahash_init(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) state->update = ahash_update_first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) state->finup = ahash_finup_first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) state->final = ahash_final_no_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) state->ctx_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) state->ctx_dma_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) state->buf_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) state->buflen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) state->next_buflen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) static int ahash_update(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) return state->update(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) static int ahash_finup(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) return state->finup(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) static int ahash_final(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) return state->final(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) static int ahash_export(struct ahash_request *req, void *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) struct caam_export_state *export = out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) u8 *buf = state->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) int len = state->buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) memcpy(export->buf, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) memcpy(export->caam_ctx, state->caam_ctx, sizeof(export->caam_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) export->buflen = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) export->update = state->update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) export->final = state->final;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) export->finup = state->finup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) static int ahash_import(struct ahash_request *req, const void *in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) struct caam_hash_state *state = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) const struct caam_export_state *export = in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) memset(state, 0, sizeof(*state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) memcpy(state->buf, export->buf, export->buflen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) memcpy(state->caam_ctx, export->caam_ctx, sizeof(state->caam_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) state->buflen = export->buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) state->update = export->update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) state->final = export->final;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) state->finup = export->finup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) struct caam_hash_template {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) char name[CRYPTO_MAX_ALG_NAME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) char driver_name[CRYPTO_MAX_ALG_NAME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) char hmac_name[CRYPTO_MAX_ALG_NAME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) char hmac_driver_name[CRYPTO_MAX_ALG_NAME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) unsigned int blocksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) struct ahash_alg template_ahash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) u32 alg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) /* ahash descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) static struct caam_hash_template driver_hash[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) .name = "sha1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) .driver_name = "sha1-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) .hmac_name = "hmac(sha1)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) .hmac_driver_name = "hmac-sha1-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) .blocksize = SHA1_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) .template_ahash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) .init = ahash_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) .update = ahash_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) .final = ahash_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) .finup = ahash_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) .digest = ahash_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) .export = ahash_export,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) .import = ahash_import,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) .setkey = ahash_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) .halg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) .digestsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) .statesize = sizeof(struct caam_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) .alg_type = OP_ALG_ALGSEL_SHA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) .name = "sha224",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) .driver_name = "sha224-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) .hmac_name = "hmac(sha224)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) .hmac_driver_name = "hmac-sha224-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) .blocksize = SHA224_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) .template_ahash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) .init = ahash_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) .update = ahash_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) .final = ahash_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) .finup = ahash_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) .digest = ahash_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) .export = ahash_export,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) .import = ahash_import,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) .setkey = ahash_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) .halg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) .digestsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) .statesize = sizeof(struct caam_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) .alg_type = OP_ALG_ALGSEL_SHA224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) .name = "sha256",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) .driver_name = "sha256-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) .hmac_name = "hmac(sha256)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) .hmac_driver_name = "hmac-sha256-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) .blocksize = SHA256_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) .template_ahash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) .init = ahash_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) .update = ahash_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) .final = ahash_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) .finup = ahash_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) .digest = ahash_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) .export = ahash_export,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) .import = ahash_import,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) .setkey = ahash_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) .halg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) .digestsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) .statesize = sizeof(struct caam_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) .alg_type = OP_ALG_ALGSEL_SHA256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) .name = "sha384",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) .driver_name = "sha384-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) .hmac_name = "hmac(sha384)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) .hmac_driver_name = "hmac-sha384-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) .blocksize = SHA384_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) .template_ahash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) .init = ahash_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) .update = ahash_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) .final = ahash_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) .finup = ahash_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) .digest = ahash_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) .export = ahash_export,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) .import = ahash_import,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) .setkey = ahash_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) .halg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) .digestsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) .statesize = sizeof(struct caam_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) .alg_type = OP_ALG_ALGSEL_SHA384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) .name = "sha512",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) .driver_name = "sha512-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) .hmac_name = "hmac(sha512)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) .hmac_driver_name = "hmac-sha512-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) .blocksize = SHA512_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) .template_ahash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) .init = ahash_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) .update = ahash_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) .final = ahash_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) .finup = ahash_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) .digest = ahash_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) .export = ahash_export,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) .import = ahash_import,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) .setkey = ahash_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) .halg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) .digestsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) .statesize = sizeof(struct caam_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) .alg_type = OP_ALG_ALGSEL_SHA512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) .name = "md5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) .driver_name = "md5-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) .hmac_name = "hmac(md5)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) .hmac_driver_name = "hmac-md5-caam-qi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) .blocksize = MD5_BLOCK_WORDS * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) .template_ahash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) .init = ahash_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) .update = ahash_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) .final = ahash_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) .finup = ahash_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) .digest = ahash_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) .export = ahash_export,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) .import = ahash_import,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) .setkey = ahash_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) .halg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) .digestsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) .statesize = sizeof(struct caam_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) .alg_type = OP_ALG_ALGSEL_MD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) struct caam_hash_alg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) int alg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) struct ahash_alg ahash_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) static int caam_hash_cra_init(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) struct crypto_alg *base = tfm->__crt_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) struct hash_alg_common *halg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) container_of(base, struct hash_alg_common, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) struct ahash_alg *alg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) container_of(halg, struct ahash_alg, halg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) struct caam_hash_alg *caam_hash =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) container_of(alg, struct caam_hash_alg, ahash_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) /* Sizes for MDHA running digests: MD5, SHA1, 224, 256, 384, 512 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) static const u8 runninglen[] = { HASH_MSG_LEN + MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) HASH_MSG_LEN + SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) HASH_MSG_LEN + 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) HASH_MSG_LEN + SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) HASH_MSG_LEN + 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) HASH_MSG_LEN + SHA512_DIGEST_SIZE };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) ctx->dev = caam_hash->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) if (alg->setkey) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) ctx->adata.key_dma = dma_map_single_attrs(ctx->dev, ctx->key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) ARRAY_SIZE(ctx->key),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) DMA_TO_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) DMA_ATTR_SKIP_CPU_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) if (dma_mapping_error(ctx->dev, ctx->adata.key_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) dev_err(ctx->dev, "unable to map key\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) dma_addr = dma_map_single_attrs(ctx->dev, ctx->flc, sizeof(ctx->flc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) DMA_BIDIRECTIONAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) DMA_ATTR_SKIP_CPU_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) if (dma_mapping_error(ctx->dev, dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) dev_err(ctx->dev, "unable to map shared descriptors\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) if (ctx->adata.key_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) dma_unmap_single_attrs(ctx->dev, ctx->adata.key_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) ARRAY_SIZE(ctx->key),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) DMA_TO_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) DMA_ATTR_SKIP_CPU_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) for (i = 0; i < HASH_NUM_OP; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) ctx->flc_dma[i] = dma_addr + i * sizeof(ctx->flc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) /* copy descriptor header template value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam_hash->alg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) ctx->ctx_len = runninglen[(ctx->adata.algtype &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) OP_ALG_ALGSEL_SUBMASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) OP_ALG_ALGSEL_SHIFT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) sizeof(struct caam_hash_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) * For keyed hash algorithms shared descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) * will be created later in setkey() callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) return alg->setkey ? 0 : ahash_set_sh_desc(ahash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) static void caam_hash_cra_exit(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) dma_unmap_single_attrs(ctx->dev, ctx->flc_dma[0], sizeof(ctx->flc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) DMA_BIDIRECTIONAL, DMA_ATTR_SKIP_CPU_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) if (ctx->adata.key_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) dma_unmap_single_attrs(ctx->dev, ctx->adata.key_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) ARRAY_SIZE(ctx->key), DMA_TO_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) DMA_ATTR_SKIP_CPU_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) static struct caam_hash_alg *caam_hash_alloc(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) struct caam_hash_template *template, bool keyed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) struct caam_hash_alg *t_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) struct ahash_alg *halg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) struct crypto_alg *alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) t_alg = kzalloc(sizeof(*t_alg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) if (!t_alg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) t_alg->ahash_alg = template->template_ahash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) halg = &t_alg->ahash_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) alg = &halg->halg.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) if (keyed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) template->hmac_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) template->hmac_driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) template->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) template->driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) t_alg->ahash_alg.setkey = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) alg->cra_module = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) alg->cra_init = caam_hash_cra_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) alg->cra_exit = caam_hash_cra_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) alg->cra_ctxsize = sizeof(struct caam_hash_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) alg->cra_priority = CAAM_CRA_PRIORITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) alg->cra_blocksize = template->blocksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) alg->cra_alignmask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) t_alg->alg_type = template->alg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) t_alg->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) return t_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) static void dpaa2_caam_fqdan_cb(struct dpaa2_io_notification_ctx *nctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) struct dpaa2_caam_priv_per_cpu *ppriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) ppriv = container_of(nctx, struct dpaa2_caam_priv_per_cpu, nctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) napi_schedule_irqoff(&ppriv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) static int __cold dpaa2_dpseci_dpio_setup(struct dpaa2_caam_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) struct device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) struct dpaa2_io_notification_ctx *nctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) struct dpaa2_caam_priv_per_cpu *ppriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) int err, i = 0, cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) for_each_online_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) ppriv = per_cpu_ptr(priv->ppriv, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) ppriv->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) nctx = &ppriv->nctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) nctx->is_cdan = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) nctx->id = ppriv->rsp_fqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) nctx->desired_cpu = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) nctx->cb = dpaa2_caam_fqdan_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) /* Register notification callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) ppriv->dpio = dpaa2_io_service_select(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) err = dpaa2_io_service_register(ppriv->dpio, nctx, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) if (unlikely(err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) dev_dbg(dev, "No affine DPIO for cpu %d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) nctx->cb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) * If no affine DPIO for this core, there's probably
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) * none available for next cores either. Signal we want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) * to retry later, in case the DPIO devices weren't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) * probed yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) err = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) ppriv->store = dpaa2_io_store_create(DPAA2_CAAM_STORE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) if (unlikely(!ppriv->store)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) dev_err(dev, "dpaa2_io_store_create() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) if (++i == priv->num_pairs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) for_each_online_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) ppriv = per_cpu_ptr(priv->ppriv, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) if (!ppriv->nctx.cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) dpaa2_io_service_deregister(ppriv->dpio, &ppriv->nctx, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) for_each_online_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) ppriv = per_cpu_ptr(priv->ppriv, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) if (!ppriv->store)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) dpaa2_io_store_destroy(ppriv->store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) static void __cold dpaa2_dpseci_dpio_free(struct dpaa2_caam_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) struct dpaa2_caam_priv_per_cpu *ppriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) int i = 0, cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) for_each_online_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) ppriv = per_cpu_ptr(priv->ppriv, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) dpaa2_io_service_deregister(ppriv->dpio, &ppriv->nctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) dpaa2_io_store_destroy(ppriv->store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) if (++i == priv->num_pairs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) static int dpaa2_dpseci_bind(struct dpaa2_caam_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) struct dpseci_rx_queue_cfg rx_queue_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) struct device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) struct fsl_mc_device *ls_dev = to_fsl_mc_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) struct dpaa2_caam_priv_per_cpu *ppriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) int err = 0, i = 0, cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) /* Configure Rx queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) for_each_online_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) ppriv = per_cpu_ptr(priv->ppriv, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) rx_queue_cfg.options = DPSECI_QUEUE_OPT_DEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) DPSECI_QUEUE_OPT_USER_CTX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) rx_queue_cfg.order_preservation_en = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) rx_queue_cfg.dest_cfg.dest_type = DPSECI_DEST_DPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) rx_queue_cfg.dest_cfg.dest_id = ppriv->nctx.dpio_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) * Rx priority (WQ) doesn't really matter, since we use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) * pull mode, i.e. volatile dequeues from specific FQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) rx_queue_cfg.dest_cfg.priority = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) rx_queue_cfg.user_ctx = ppriv->nctx.qman64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) err = dpseci_set_rx_queue(priv->mc_io, 0, ls_dev->mc_handle, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) &rx_queue_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) dev_err(dev, "dpseci_set_rx_queue() failed with err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) if (++i == priv->num_pairs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) static void dpaa2_dpseci_congestion_free(struct dpaa2_caam_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) struct device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) if (!priv->cscn_mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) dma_unmap_single(dev, priv->cscn_dma, DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) kfree(priv->cscn_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) static void dpaa2_dpseci_free(struct dpaa2_caam_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) struct device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) struct fsl_mc_device *ls_dev = to_fsl_mc_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) if (DPSECI_VER(priv->major_ver, priv->minor_ver) > DPSECI_VER(5, 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) err = dpseci_reset(priv->mc_io, 0, ls_dev->mc_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) dev_err(dev, "dpseci_reset() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) dpaa2_dpseci_congestion_free(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) dpseci_close(priv->mc_io, 0, ls_dev->mc_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) static void dpaa2_caam_process_fd(struct dpaa2_caam_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) const struct dpaa2_fd *fd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) struct caam_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) u32 fd_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) if (dpaa2_fd_get_format(fd) != dpaa2_fd_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) dev_err(priv->dev, "Only Frame List FD format is supported!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) fd_err = dpaa2_fd_get_ctrl(fd) & FD_CTRL_ERR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) if (unlikely(fd_err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) dev_err_ratelimited(priv->dev, "FD error: %08x\n", fd_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) * FD[ADDR] is guaranteed to be valid, irrespective of errors reported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) * in FD[ERR] or FD[FRC].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) req = dpaa2_caam_iova_to_virt(priv, dpaa2_fd_get_addr(fd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) dma_unmap_single(priv->dev, req->fd_flt_dma, sizeof(req->fd_flt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) req->cbk(req->ctx, dpaa2_fd_get_frc(fd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) static int dpaa2_caam_pull_fq(struct dpaa2_caam_priv_per_cpu *ppriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) /* Retry while portal is busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) err = dpaa2_io_service_pull_fq(ppriv->dpio, ppriv->rsp_fqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) ppriv->store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) } while (err == -EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) if (unlikely(err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) dev_err(ppriv->priv->dev, "dpaa2_io_service_pull err %d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) static int dpaa2_caam_store_consume(struct dpaa2_caam_priv_per_cpu *ppriv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) struct dpaa2_dq *dq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) int cleaned = 0, is_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) dq = dpaa2_io_store_next(ppriv->store, &is_last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) if (unlikely(!dq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) if (unlikely(!is_last)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) dev_dbg(ppriv->priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) "FQ %d returned no valid frames\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) ppriv->rsp_fqid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) * MUST retry until we get some sort of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) * valid response token (be it "empty dequeue"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) * or a valid frame).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) /* Process FD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) dpaa2_caam_process_fd(ppriv->priv, dpaa2_dq_fd(dq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) cleaned++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) } while (!is_last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) return cleaned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) static int dpaa2_dpseci_poll(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) struct dpaa2_caam_priv_per_cpu *ppriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) struct dpaa2_caam_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) int err, cleaned = 0, store_cleaned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) ppriv = container_of(napi, struct dpaa2_caam_priv_per_cpu, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) priv = ppriv->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) if (unlikely(dpaa2_caam_pull_fq(ppriv)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) store_cleaned = dpaa2_caam_store_consume(ppriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) cleaned += store_cleaned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) if (store_cleaned == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) cleaned > budget - DPAA2_CAAM_STORE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) /* Try to dequeue some more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) err = dpaa2_caam_pull_fq(ppriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) if (unlikely(err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) if (cleaned < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) napi_complete_done(napi, cleaned);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) err = dpaa2_io_service_rearm(ppriv->dpio, &ppriv->nctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) if (unlikely(err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) dev_err(priv->dev, "Notification rearm failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) return cleaned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) static int dpaa2_dpseci_congestion_setup(struct dpaa2_caam_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) u16 token)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) struct dpseci_congestion_notification_cfg cong_notif_cfg = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) struct device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) * Congestion group feature supported starting with DPSECI API v5.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) * and only when object has been created with this capability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) if ((DPSECI_VER(priv->major_ver, priv->minor_ver) < DPSECI_VER(5, 1)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) !(priv->dpseci_attr.options & DPSECI_OPT_HAS_CG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) priv->cscn_mem = kzalloc(DPAA2_CSCN_SIZE + DPAA2_CSCN_ALIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) GFP_KERNEL | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) if (!priv->cscn_mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) priv->cscn_mem_aligned = PTR_ALIGN(priv->cscn_mem, DPAA2_CSCN_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) priv->cscn_dma = dma_map_single(dev, priv->cscn_mem_aligned,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) if (dma_mapping_error(dev, priv->cscn_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) dev_err(dev, "Error mapping CSCN memory area\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) goto err_dma_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) cong_notif_cfg.units = DPSECI_CONGESTION_UNIT_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) cong_notif_cfg.threshold_entry = DPAA2_SEC_CONG_ENTRY_THRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) cong_notif_cfg.threshold_exit = DPAA2_SEC_CONG_EXIT_THRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) cong_notif_cfg.message_ctx = (uintptr_t)priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) cong_notif_cfg.message_iova = priv->cscn_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) cong_notif_cfg.notification_mode = DPSECI_CGN_MODE_WRITE_MEM_ON_ENTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) DPSECI_CGN_MODE_WRITE_MEM_ON_EXIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) DPSECI_CGN_MODE_COHERENT_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) err = dpseci_set_congestion_notification(priv->mc_io, 0, token,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) &cong_notif_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) dev_err(dev, "dpseci_set_congestion_notification failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) goto err_set_cong;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) err_set_cong:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) dma_unmap_single(dev, priv->cscn_dma, DPAA2_CSCN_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) err_dma_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) kfree(priv->cscn_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) static int __cold dpaa2_dpseci_setup(struct fsl_mc_device *ls_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) struct device *dev = &ls_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) struct dpaa2_caam_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) struct dpaa2_caam_priv_per_cpu *ppriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) int err, cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) priv->dpsec_id = ls_dev->obj_desc.id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) /* Get a handle for the DPSECI this interface is associate with */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) err = dpseci_open(priv->mc_io, 0, priv->dpsec_id, &ls_dev->mc_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) dev_err(dev, "dpseci_open() failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) goto err_open;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) err = dpseci_get_api_version(priv->mc_io, 0, &priv->major_ver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) &priv->minor_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) dev_err(dev, "dpseci_get_api_version() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) goto err_get_vers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) dev_info(dev, "dpseci v%d.%d\n", priv->major_ver, priv->minor_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) if (DPSECI_VER(priv->major_ver, priv->minor_ver) > DPSECI_VER(5, 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) err = dpseci_reset(priv->mc_io, 0, ls_dev->mc_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) dev_err(dev, "dpseci_reset() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) goto err_get_vers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) err = dpseci_get_attributes(priv->mc_io, 0, ls_dev->mc_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) &priv->dpseci_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) dev_err(dev, "dpseci_get_attributes() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) goto err_get_vers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) err = dpseci_get_sec_attr(priv->mc_io, 0, ls_dev->mc_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) &priv->sec_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) dev_err(dev, "dpseci_get_sec_attr() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) goto err_get_vers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) err = dpaa2_dpseci_congestion_setup(priv, ls_dev->mc_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) dev_err(dev, "setup_congestion() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) goto err_get_vers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) priv->num_pairs = min(priv->dpseci_attr.num_rx_queues,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) priv->dpseci_attr.num_tx_queues);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) if (priv->num_pairs > num_online_cpus()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) dev_warn(dev, "%d queues won't be used\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) priv->num_pairs - num_online_cpus());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) priv->num_pairs = num_online_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) for (i = 0; i < priv->dpseci_attr.num_rx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) err = dpseci_get_rx_queue(priv->mc_io, 0, ls_dev->mc_handle, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) &priv->rx_queue_attr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) dev_err(dev, "dpseci_get_rx_queue() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) goto err_get_rx_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) for (i = 0; i < priv->dpseci_attr.num_tx_queues; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) err = dpseci_get_tx_queue(priv->mc_io, 0, ls_dev->mc_handle, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) &priv->tx_queue_attr[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) dev_err(dev, "dpseci_get_tx_queue() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) goto err_get_rx_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) for_each_online_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) u8 j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) j = i % priv->num_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) ppriv = per_cpu_ptr(priv->ppriv, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) ppriv->req_fqid = priv->tx_queue_attr[j].fqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) * Allow all cores to enqueue, while only some of them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) * will take part in dequeuing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) if (++i > priv->num_pairs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) ppriv->rsp_fqid = priv->rx_queue_attr[j].fqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) ppriv->prio = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) dev_dbg(dev, "pair %d: rx queue %d, tx queue %d\n", j,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) priv->rx_queue_attr[j].fqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) priv->tx_queue_attr[j].fqid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) ppriv->net_dev.dev = *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) INIT_LIST_HEAD(&ppriv->net_dev.napi_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) netif_napi_add(&ppriv->net_dev, &ppriv->napi, dpaa2_dpseci_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) DPAA2_CAAM_NAPI_WEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) err_get_rx_queue:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) dpaa2_dpseci_congestion_free(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) err_get_vers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) dpseci_close(priv->mc_io, 0, ls_dev->mc_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) err_open:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) static int dpaa2_dpseci_enable(struct dpaa2_caam_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) struct device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) struct fsl_mc_device *ls_dev = to_fsl_mc_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) struct dpaa2_caam_priv_per_cpu *ppriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) for (i = 0; i < priv->num_pairs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) ppriv = per_cpu_ptr(priv->ppriv, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) napi_enable(&ppriv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) return dpseci_enable(priv->mc_io, 0, ls_dev->mc_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) static int __cold dpaa2_dpseci_disable(struct dpaa2_caam_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) struct device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) struct dpaa2_caam_priv_per_cpu *ppriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) struct fsl_mc_device *ls_dev = to_fsl_mc_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) int i, err = 0, enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) err = dpseci_disable(priv->mc_io, 0, ls_dev->mc_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) dev_err(dev, "dpseci_disable() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) err = dpseci_is_enabled(priv->mc_io, 0, ls_dev->mc_handle, &enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) dev_err(dev, "dpseci_is_enabled() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) dev_dbg(dev, "disable: %s\n", enabled ? "false" : "true");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) for (i = 0; i < priv->num_pairs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) ppriv = per_cpu_ptr(priv->ppriv, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) napi_disable(&ppriv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) netif_napi_del(&ppriv->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) static struct list_head hash_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) static int dpaa2_caam_probe(struct fsl_mc_device *dpseci_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) struct dpaa2_caam_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) int i, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) bool registered = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) * There is no way to get CAAM endianness - there is no direct register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) * space access and MC f/w does not provide this attribute.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) * All DPAA2-based SoCs have little endian CAAM, thus hard-code this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) * property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) caam_little_end = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) caam_imx = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) dev = &dpseci_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) dev_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) priv->domain = iommu_get_domain_for_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) qi_cache = kmem_cache_create("dpaa2_caamqicache", CAAM_QI_MEMCACHE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) 0, SLAB_CACHE_DMA, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) if (!qi_cache) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) dev_err(dev, "Can't allocate SEC cache\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(49));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) dev_err(dev, "dma_set_mask_and_coherent() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) goto err_dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) /* Obtain a MC portal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) err = fsl_mc_portal_allocate(dpseci_dev, 0, &priv->mc_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) if (err == -ENXIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) err = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) dev_err(dev, "MC portal allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) goto err_dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) priv->ppriv = alloc_percpu(*priv->ppriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) if (!priv->ppriv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) dev_err(dev, "alloc_percpu() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) goto err_alloc_ppriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) /* DPSECI initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) err = dpaa2_dpseci_setup(dpseci_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) dev_err(dev, "dpaa2_dpseci_setup() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) goto err_dpseci_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) /* DPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) err = dpaa2_dpseci_dpio_setup(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) dev_err_probe(dev, err, "dpaa2_dpseci_dpio_setup() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) goto err_dpio_setup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) /* DPSECI binding to DPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) err = dpaa2_dpseci_bind(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) dev_err(dev, "dpaa2_dpseci_bind() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) goto err_bind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) /* DPSECI enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) err = dpaa2_dpseci_enable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) dev_err(dev, "dpaa2_dpseci_enable() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) goto err_bind;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) dpaa2_dpseci_debugfs_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) /* register crypto algorithms the device supports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) struct caam_skcipher_alg *t_alg = driver_algs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) u32 alg_sel = t_alg->caam.class1_alg_type & OP_ALG_ALGSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) /* Skip DES algorithms if not supported by device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) if (!priv->sec_attr.des_acc_num &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) (alg_sel == OP_ALG_ALGSEL_3DES ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) alg_sel == OP_ALG_ALGSEL_DES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) /* Skip AES algorithms if not supported by device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) if (!priv->sec_attr.aes_acc_num &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) alg_sel == OP_ALG_ALGSEL_AES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) /* Skip CHACHA20 algorithms if not supported by device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) if (alg_sel == OP_ALG_ALGSEL_CHACHA20 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) !priv->sec_attr.ccha_acc_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) t_alg->caam.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) caam_skcipher_alg_init(t_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) err = crypto_register_skcipher(&t_alg->skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) dev_warn(dev, "%s alg registration failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) t_alg->skcipher.base.cra_driver_name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) t_alg->registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) struct caam_aead_alg *t_alg = driver_aeads + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) u32 c1_alg_sel = t_alg->caam.class1_alg_type &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) OP_ALG_ALGSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) u32 c2_alg_sel = t_alg->caam.class2_alg_type &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) OP_ALG_ALGSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) /* Skip DES algorithms if not supported by device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) if (!priv->sec_attr.des_acc_num &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) (c1_alg_sel == OP_ALG_ALGSEL_3DES ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) c1_alg_sel == OP_ALG_ALGSEL_DES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) /* Skip AES algorithms if not supported by device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) if (!priv->sec_attr.aes_acc_num &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) c1_alg_sel == OP_ALG_ALGSEL_AES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) /* Skip CHACHA20 algorithms if not supported by device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) if (c1_alg_sel == OP_ALG_ALGSEL_CHACHA20 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) !priv->sec_attr.ccha_acc_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) /* Skip POLY1305 algorithms if not supported by device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) if (c2_alg_sel == OP_ALG_ALGSEL_POLY1305 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) !priv->sec_attr.ptha_acc_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) * Skip algorithms requiring message digests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) * if MD not supported by device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) if ((c2_alg_sel & ~OP_ALG_ALGSEL_SUBMASK) == 0x40 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) !priv->sec_attr.md_acc_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) t_alg->caam.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) caam_aead_alg_init(t_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) err = crypto_register_aead(&t_alg->aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) dev_warn(dev, "%s alg registration failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) t_alg->aead.base.cra_driver_name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) t_alg->registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) if (registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) dev_info(dev, "algorithms registered in /proc/crypto\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) /* register hash algorithms the device supports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) INIT_LIST_HEAD(&hash_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) * Skip registration of any hashing algorithms if MD block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) * is not present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) if (!priv->sec_attr.md_acc_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) for (i = 0; i < ARRAY_SIZE(driver_hash); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) struct caam_hash_alg *t_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) struct caam_hash_template *alg = driver_hash + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) /* register hmac version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) t_alg = caam_hash_alloc(dev, alg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) if (IS_ERR(t_alg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) err = PTR_ERR(t_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) dev_warn(dev, "%s hash alg allocation failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) alg->hmac_driver_name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) err = crypto_register_ahash(&t_alg->ahash_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) dev_warn(dev, "%s alg registration failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) t_alg->ahash_alg.halg.base.cra_driver_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) kfree(t_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) list_add_tail(&t_alg->entry, &hash_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) /* register unkeyed version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) t_alg = caam_hash_alloc(dev, alg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) if (IS_ERR(t_alg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) err = PTR_ERR(t_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) dev_warn(dev, "%s alg allocation failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) alg->driver_name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) err = crypto_register_ahash(&t_alg->ahash_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) dev_warn(dev, "%s alg registration failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) t_alg->ahash_alg.halg.base.cra_driver_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) kfree(t_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) list_add_tail(&t_alg->entry, &hash_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) if (!list_empty(&hash_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) dev_info(dev, "hash algorithms registered in /proc/crypto\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) err_bind:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) dpaa2_dpseci_dpio_free(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) err_dpio_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) dpaa2_dpseci_free(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) err_dpseci_setup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) free_percpu(priv->ppriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) err_alloc_ppriv:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) fsl_mc_portal_free(priv->mc_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) err_dma_mask:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) kmem_cache_destroy(qi_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) static int __cold dpaa2_caam_remove(struct fsl_mc_device *ls_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) struct dpaa2_caam_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) dev = &ls_dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) dpaa2_dpseci_debugfs_exit(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) struct caam_aead_alg *t_alg = driver_aeads + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) if (t_alg->registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) crypto_unregister_aead(&t_alg->aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) struct caam_skcipher_alg *t_alg = driver_algs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) if (t_alg->registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) crypto_unregister_skcipher(&t_alg->skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) if (hash_list.next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) struct caam_hash_alg *t_hash_alg, *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) list_for_each_entry_safe(t_hash_alg, p, &hash_list, entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) crypto_unregister_ahash(&t_hash_alg->ahash_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) list_del(&t_hash_alg->entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) kfree(t_hash_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) dpaa2_dpseci_disable(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) dpaa2_dpseci_dpio_free(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) dpaa2_dpseci_free(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) free_percpu(priv->ppriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) fsl_mc_portal_free(priv->mc_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) kmem_cache_destroy(qi_cache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) int dpaa2_caam_enqueue(struct device *dev, struct caam_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) struct dpaa2_fd fd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) struct dpaa2_caam_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) struct dpaa2_caam_priv_per_cpu *ppriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) int err = 0, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) if (IS_ERR(req))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) return PTR_ERR(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) if (priv->cscn_mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) dma_sync_single_for_cpu(priv->dev, priv->cscn_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) DPAA2_CSCN_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) if (unlikely(dpaa2_cscn_state_congested(priv->cscn_mem_aligned))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) dev_dbg_ratelimited(dev, "Dropping request\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) dpaa2_fl_set_flc(&req->fd_flt[1], req->flc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) req->fd_flt_dma = dma_map_single(dev, req->fd_flt, sizeof(req->fd_flt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) if (dma_mapping_error(dev, req->fd_flt_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) dev_err(dev, "DMA mapping error for QI enqueue request\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) memset(&fd, 0, sizeof(fd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) dpaa2_fd_set_format(&fd, dpaa2_fd_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) dpaa2_fd_set_addr(&fd, req->fd_flt_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) dpaa2_fd_set_len(&fd, dpaa2_fl_get_len(&req->fd_flt[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) dpaa2_fd_set_flc(&fd, req->flc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) ppriv = raw_cpu_ptr(priv->ppriv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) for (i = 0; i < (priv->dpseci_attr.num_tx_queues << 1); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) err = dpaa2_io_service_enqueue_fq(ppriv->dpio, ppriv->req_fqid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) &fd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) if (err != -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) if (unlikely(err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) dev_err_ratelimited(dev, "Error enqueuing frame: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) return -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) dma_unmap_single(dev, req->fd_flt_dma, sizeof(req->fd_flt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) EXPORT_SYMBOL(dpaa2_caam_enqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) static const struct fsl_mc_device_id dpaa2_caam_match_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) .vendor = FSL_MC_VENDOR_FREESCALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) .obj_type = "dpseci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) { .vendor = 0x0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) MODULE_DEVICE_TABLE(fslmc, dpaa2_caam_match_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) static struct fsl_mc_driver dpaa2_caam_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) .probe = dpaa2_caam_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) .remove = dpaa2_caam_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) .match_id_table = dpaa2_caam_match_id_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) MODULE_LICENSE("Dual BSD/GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) MODULE_AUTHOR("Freescale Semiconductor, Inc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) MODULE_DESCRIPTION("Freescale DPAA2 CAAM Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) module_fsl_mc_driver(dpaa2_caam_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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