^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale FSL CAAM support for crypto API over QI backend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Based on caamalg.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2013-2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2016-2019 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "compat.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "ctrl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "intern.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "desc_constr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "error.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "sg_sw_qm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "key_gen.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "qi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "jr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "caamalg_desc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <crypto/xts.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * crypto alg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CAAM_CRA_PRIORITY 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* max key is sum of AES_MAX_KEY_SIZE, max split key size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CAAM_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) SHA512_DIGEST_SIZE * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DESC_MAX_USED_BYTES (DESC_QI_AEAD_GIVENC_LEN + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) CAAM_MAX_KEY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DESC_MAX_USED_LEN (DESC_MAX_USED_BYTES / CAAM_CMD_SZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct caam_alg_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int class1_alg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int class2_alg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bool rfc3686;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) bool geniv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) bool nodkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct caam_aead_alg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct aead_alg aead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct caam_alg_entry caam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) bool registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct caam_skcipher_alg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct skcipher_alg skcipher;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct caam_alg_entry caam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) bool registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * per-session context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct caam_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct device *jrdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 sh_desc_enc[DESC_MAX_USED_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 sh_desc_dec[DESC_MAX_USED_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 key[CAAM_MAX_KEY_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dma_addr_t key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) enum dma_data_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct alginfo adata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct alginfo cdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct device *qidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) spinlock_t lock; /* Protects multiple init of driver context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct caam_drv_ctx *drv_ctx[NUM_OP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) bool xts_key_fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct crypto_skcipher *fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct caam_skcipher_req_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct skcipher_request fallback_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static int aead_set_sh_desc(struct crypto_aead *aead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) typeof(*alg), aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int ivsize = crypto_aead_ivsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 ctx1_iv_off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 *nonce = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int data_len[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 inl_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) const bool ctr_mode = ((ctx->cdata.algtype & OP_ALG_AAI_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) OP_ALG_AAI_CTR_MOD128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const bool is_rfc3686 = alg->caam.rfc3686;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (!ctx->cdata.keylen || !ctx->authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * AES-CTR needs to load IV in CONTEXT1 reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * at an offset of 128bits (16bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * CONTEXT1[255:128] = IV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ctr_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ctx1_iv_off = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * RFC3686 specific:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * CONTEXT1[255:128] = {NONCE, IV, COUNTER}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (is_rfc3686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) nonce = (u32 *)((void *)ctx->key + ctx->adata.keylen_pad +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ctx->cdata.keylen - CTR_RFC3686_NONCE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * In case |user key| > |derived key|, using DKP<imm,imm> would result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * in invalid opcodes (last bytes of user key) in the resulting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * descriptor. Use DKP<ptr,imm> instead => both virtual and dma key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * addresses are needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ctx->adata.key_virt = ctx->key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ctx->adata.key_dma = ctx->key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ctx->cdata.key_virt = ctx->key + ctx->adata.keylen_pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ctx->cdata.key_dma = ctx->key_dma + ctx->adata.keylen_pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) data_len[0] = ctx->adata.keylen_pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) data_len[1] = ctx->cdata.keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (alg->caam.geniv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) goto skip_enc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* aead_encrypt shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (desc_inline_query(DESC_QI_AEAD_ENC_LEN +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DESC_JOB_IO_LEN, data_len, &inl_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ARRAY_SIZE(data_len)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ctx->adata.key_inline = !!(inl_mask & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ctx->cdata.key_inline = !!(inl_mask & 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) cnstr_shdsc_aead_encap(ctx->sh_desc_enc, &ctx->cdata, &ctx->adata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ivsize, ctx->authsize, is_rfc3686, nonce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ctx1_iv_off, true, ctrlpriv->era);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) skip_enc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* aead_decrypt shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (desc_inline_query(DESC_QI_AEAD_DEC_LEN +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DESC_JOB_IO_LEN, data_len, &inl_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ARRAY_SIZE(data_len)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ctx->adata.key_inline = !!(inl_mask & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ctx->cdata.key_inline = !!(inl_mask & 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) cnstr_shdsc_aead_decap(ctx->sh_desc_dec, &ctx->cdata, &ctx->adata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ivsize, ctx->authsize, alg->caam.geniv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) is_rfc3686, nonce, ctx1_iv_off, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ctrlpriv->era);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!alg->caam.geniv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) goto skip_givenc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* aead_givencrypt shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (desc_inline_query(DESC_QI_AEAD_GIVENC_LEN +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) DESC_JOB_IO_LEN, data_len, &inl_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ARRAY_SIZE(data_len)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ctx->adata.key_inline = !!(inl_mask & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ctx->cdata.key_inline = !!(inl_mask & 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) cnstr_shdsc_aead_givencap(ctx->sh_desc_enc, &ctx->cdata, &ctx->adata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ivsize, ctx->authsize, is_rfc3686, nonce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ctx1_iv_off, true, ctrlpriv->era);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) skip_givenc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int aead_setauthsize(struct crypto_aead *authenc, unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct caam_ctx *ctx = crypto_aead_ctx(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ctx->authsize = authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) aead_set_sh_desc(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int aead_setkey(struct crypto_aead *aead, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct device *jrdev = ctx->jrdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct crypto_authenc_keys keys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) goto badkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_dbg(jrdev, "keylen %d enckeylen %d authkeylen %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) keys.authkeylen + keys.enckeylen, keys.enckeylen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) keys.authkeylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) print_hex_dump_debug("key in @" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * If DKP is supported, use it in the shared descriptor to generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * the split key.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (ctrlpriv->era >= 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ctx->adata.keylen = keys.authkeylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ctx->adata.keylen_pad = split_key_len(ctx->adata.algtype &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) OP_ALG_ALGSEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ctx->adata.keylen_pad + keys.enckeylen > CAAM_MAX_KEY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) goto badkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) memcpy(ctx->key, keys.authkey, keys.authkeylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) keys.enckeylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dma_sync_single_for_device(jrdev->parent, ctx->key_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ctx->adata.keylen_pad +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) keys.enckeylen, ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) goto skip_split_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = gen_split_key(jrdev, ctx->key, &ctx->adata, keys.authkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) keys.authkeylen, CAAM_MAX_KEY_SIZE -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) keys.enckeylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) goto badkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* postpend encryption key to auth split key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) memcpy(ctx->key + ctx->adata.keylen_pad, keys.enckey, keys.enckeylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dma_sync_single_for_device(jrdev->parent, ctx->key_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ctx->adata.keylen_pad + keys.enckeylen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) print_hex_dump_debug("ctx.key@" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ctx->adata.keylen_pad + keys.enckeylen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) skip_split_key:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ctx->cdata.keylen = keys.enckeylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = aead_set_sh_desc(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) goto badkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Now update the driver contexts with the new shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ctx->drv_ctx[ENCRYPT]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ctx->sh_desc_enc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_err(jrdev, "driver enc context update failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) goto badkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ctx->drv_ctx[DECRYPT]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ctx->sh_desc_dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_err(jrdev, "driver dec context update failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) goto badkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) memzero_explicit(&keys, sizeof(keys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) badkey:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) memzero_explicit(&keys, sizeof(keys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int des3_aead_setkey(struct crypto_aead *aead, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct crypto_authenc_keys keys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) err = crypto_authenc_extractkeys(&keys, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (unlikely(err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) err = verify_aead_des3_key(aead, keys.enckey, keys.enckeylen) ?:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) aead_setkey(aead, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) memzero_explicit(&keys, sizeof(keys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int gcm_set_sh_desc(struct crypto_aead *aead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int ivsize = crypto_aead_ivsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ctx->cdata.keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (!ctx->cdata.keylen || !ctx->authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * Job Descriptor and Shared Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * must fit into the 64-word Descriptor h/w Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (rem_bytes >= DESC_QI_GCM_ENC_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ctx->cdata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ctx->cdata.key_virt = ctx->key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ctx->cdata.key_inline = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ctx->cdata.key_dma = ctx->key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) cnstr_shdsc_gcm_encap(ctx->sh_desc_enc, &ctx->cdata, ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ctx->authsize, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * Job Descriptor and Shared Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * must fit into the 64-word Descriptor h/w Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (rem_bytes >= DESC_QI_GCM_DEC_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ctx->cdata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ctx->cdata.key_virt = ctx->key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ctx->cdata.key_inline = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ctx->cdata.key_dma = ctx->key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) cnstr_shdsc_gcm_decap(ctx->sh_desc_dec, &ctx->cdata, ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ctx->authsize, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int gcm_setauthsize(struct crypto_aead *authenc, unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct caam_ctx *ctx = crypto_aead_ctx(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) err = crypto_gcm_check_authsize(authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ctx->authsize = authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) gcm_set_sh_desc(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int gcm_setkey(struct crypto_aead *aead,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct device *jrdev = ctx->jrdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret = aes_check_keylen(keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) print_hex_dump_debug("key in @" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) memcpy(ctx->key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dma_sync_single_for_device(jrdev->parent, ctx->key_dma, keylen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ctx->cdata.keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = gcm_set_sh_desc(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Now update the driver contexts with the new shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (ctx->drv_ctx[ENCRYPT]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ctx->sh_desc_enc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dev_err(jrdev, "driver enc context update failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (ctx->drv_ctx[DECRYPT]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ctx->sh_desc_dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(jrdev, "driver dec context update failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int rfc4106_set_sh_desc(struct crypto_aead *aead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned int ivsize = crypto_aead_ivsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ctx->cdata.keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!ctx->cdata.keylen || !ctx->authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ctx->cdata.key_virt = ctx->key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * Job Descriptor and Shared Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * must fit into the 64-word Descriptor h/w Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (rem_bytes >= DESC_QI_RFC4106_ENC_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ctx->cdata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ctx->cdata.key_inline = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ctx->cdata.key_dma = ctx->key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) cnstr_shdsc_rfc4106_encap(ctx->sh_desc_enc, &ctx->cdata, ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ctx->authsize, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * Job Descriptor and Shared Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * must fit into the 64-word Descriptor h/w Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (rem_bytes >= DESC_QI_RFC4106_DEC_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ctx->cdata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ctx->cdata.key_inline = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ctx->cdata.key_dma = ctx->key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) cnstr_shdsc_rfc4106_decap(ctx->sh_desc_dec, &ctx->cdata, ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ctx->authsize, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int rfc4106_setauthsize(struct crypto_aead *authenc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct caam_ctx *ctx = crypto_aead_ctx(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) err = crypto_rfc4106_check_authsize(authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ctx->authsize = authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) rfc4106_set_sh_desc(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int rfc4106_setkey(struct crypto_aead *aead,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct device *jrdev = ctx->jrdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = aes_check_keylen(keylen - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) print_hex_dump_debug("key in @" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) memcpy(ctx->key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * The last four bytes of the key material are used as the salt value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * in the nonce. Update the AES key length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ctx->cdata.keylen = keylen - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dma_sync_single_for_device(jrdev->parent, ctx->key_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ctx->cdata.keylen, ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret = rfc4106_set_sh_desc(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Now update the driver contexts with the new shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (ctx->drv_ctx[ENCRYPT]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ctx->sh_desc_enc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dev_err(jrdev, "driver enc context update failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (ctx->drv_ctx[DECRYPT]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ctx->sh_desc_dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_err(jrdev, "driver dec context update failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int rfc4543_set_sh_desc(struct crypto_aead *aead)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) unsigned int ivsize = crypto_aead_ivsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int rem_bytes = CAAM_DESC_BYTES_MAX - DESC_JOB_IO_LEN -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ctx->cdata.keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (!ctx->cdata.keylen || !ctx->authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ctx->cdata.key_virt = ctx->key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * Job Descriptor and Shared Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * must fit into the 64-word Descriptor h/w Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (rem_bytes >= DESC_QI_RFC4543_ENC_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ctx->cdata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ctx->cdata.key_inline = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ctx->cdata.key_dma = ctx->key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) cnstr_shdsc_rfc4543_encap(ctx->sh_desc_enc, &ctx->cdata, ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ctx->authsize, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * Job Descriptor and Shared Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * must fit into the 64-word Descriptor h/w Buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (rem_bytes >= DESC_QI_RFC4543_DEC_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ctx->cdata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ctx->cdata.key_inline = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ctx->cdata.key_dma = ctx->key_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) cnstr_shdsc_rfc4543_decap(ctx->sh_desc_dec, &ctx->cdata, ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ctx->authsize, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int rfc4543_setauthsize(struct crypto_aead *authenc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct caam_ctx *ctx = crypto_aead_ctx(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (authsize != 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ctx->authsize = authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) rfc4543_set_sh_desc(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int rfc4543_setkey(struct crypto_aead *aead,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct device *jrdev = ctx->jrdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = aes_check_keylen(keylen - 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) print_hex_dump_debug("key in @" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) memcpy(ctx->key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * The last four bytes of the key material are used as the salt value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * in the nonce. Update the AES key length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ctx->cdata.keylen = keylen - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dma_sync_single_for_device(jrdev->parent, ctx->key_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ctx->cdata.keylen, ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ret = rfc4543_set_sh_desc(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Now update the driver contexts with the new shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (ctx->drv_ctx[ENCRYPT]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ctx->sh_desc_enc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev_err(jrdev, "driver enc context update failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (ctx->drv_ctx[DECRYPT]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ctx->sh_desc_dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dev_err(jrdev, "driver dec context update failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) unsigned int keylen, const u32 ctx1_iv_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct caam_skcipher_alg *alg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) container_of(crypto_skcipher_alg(skcipher), typeof(*alg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct device *jrdev = ctx->jrdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) unsigned int ivsize = crypto_skcipher_ivsize(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) const bool is_rfc3686 = alg->caam.rfc3686;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) print_hex_dump_debug("key in @" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ctx->cdata.keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ctx->cdata.key_virt = key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ctx->cdata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* skcipher encrypt, decrypt shared descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) cnstr_shdsc_skcipher_encap(ctx->sh_desc_enc, &ctx->cdata, ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) is_rfc3686, ctx1_iv_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) cnstr_shdsc_skcipher_decap(ctx->sh_desc_dec, &ctx->cdata, ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) is_rfc3686, ctx1_iv_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* Now update the driver contexts with the new shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (ctx->drv_ctx[ENCRYPT]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ctx->sh_desc_enc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dev_err(jrdev, "driver enc context update failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (ctx->drv_ctx[DECRYPT]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ctx->sh_desc_dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dev_err(jrdev, "driver dec context update failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static int aes_skcipher_setkey(struct crypto_skcipher *skcipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) err = aes_check_keylen(keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return skcipher_setkey(skcipher, key, keylen, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static int rfc3686_skcipher_setkey(struct crypto_skcipher *skcipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u32 ctx1_iv_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * RFC3686 specific:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * | CONTEXT1[255:128] = {NONCE, IV, COUNTER}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * | *key = {KEY, NONCE}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) keylen -= CTR_RFC3686_NONCE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) err = aes_check_keylen(keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return skcipher_setkey(skcipher, key, keylen, ctx1_iv_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static int ctr_skcipher_setkey(struct crypto_skcipher *skcipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) u32 ctx1_iv_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * AES-CTR needs to load IV in CONTEXT1 reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * at an offset of 128bits (16bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * CONTEXT1[255:128] = IV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ctx1_iv_off = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) err = aes_check_keylen(keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return skcipher_setkey(skcipher, key, keylen, ctx1_iv_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int des3_skcipher_setkey(struct crypto_skcipher *skcipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return verify_skcipher_des3_key(skcipher, key) ?:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) skcipher_setkey(skcipher, key, keylen, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int des_skcipher_setkey(struct crypto_skcipher *skcipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return verify_skcipher_des_key(skcipher, key) ?:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) skcipher_setkey(skcipher, key, keylen, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static int xts_skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct device *jrdev = ctx->jrdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct caam_drv_private *ctrlpriv = dev_get_drvdata(jrdev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) err = xts_verify_key(skcipher, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_dbg(jrdev, "key size mismatch\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (keylen != 2 * AES_KEYSIZE_128 && keylen != 2 * AES_KEYSIZE_256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ctx->xts_key_fallback = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (ctrlpriv->era <= 8 || ctx->xts_key_fallback) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) err = crypto_skcipher_setkey(ctx->fallback, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ctx->cdata.keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ctx->cdata.key_virt = key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ctx->cdata.key_inline = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* xts skcipher encrypt, decrypt shared descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) cnstr_shdsc_xts_skcipher_encap(ctx->sh_desc_enc, &ctx->cdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) cnstr_shdsc_xts_skcipher_decap(ctx->sh_desc_dec, &ctx->cdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* Now update the driver contexts with the new shared descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (ctx->drv_ctx[ENCRYPT]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ret = caam_drv_ctx_update(ctx->drv_ctx[ENCRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ctx->sh_desc_enc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) dev_err(jrdev, "driver enc context update failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (ctx->drv_ctx[DECRYPT]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ret = caam_drv_ctx_update(ctx->drv_ctx[DECRYPT],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ctx->sh_desc_dec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dev_err(jrdev, "driver dec context update failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * aead_edesc - s/w-extended aead descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * @src_nents: number of segments in input scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * @dst_nents: number of segments in output scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * @iv_dma: dma address of iv for checking continuity and link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * @qm_sg_bytes: length of dma mapped h/w link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * @qm_sg_dma: bus physical mapped address of h/w link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * @assoclen: associated data length, in CAAM endianness
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * @assoclen_dma: bus physical mapped address of req->assoclen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * @drv_req: driver-specific request structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * @sgt: the h/w link table, followed by IV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct aead_edesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) int dst_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dma_addr_t iv_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dma_addr_t qm_sg_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) unsigned int assoclen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) dma_addr_t assoclen_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct caam_drv_req drv_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct qm_sg_entry sgt[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * skcipher_edesc - s/w-extended skcipher descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * @src_nents: number of segments in input scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * @dst_nents: number of segments in output scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * @iv_dma: dma address of iv for checking continuity and link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * @qm_sg_bytes: length of dma mapped h/w link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * @qm_sg_dma: bus physical mapped address of h/w link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * @drv_req: driver-specific request structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * @sgt: the h/w link table, followed by IV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct skcipher_edesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) int src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int dst_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) dma_addr_t iv_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) dma_addr_t qm_sg_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct caam_drv_req drv_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct qm_sg_entry sgt[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static struct caam_drv_ctx *get_drv_ctx(struct caam_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) enum optype type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * This function is called on the fast path with values of 'type'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * known at compile time. Invalid arguments are not expected and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * thus no checks are made.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct caam_drv_ctx *drv_ctx = ctx->drv_ctx[type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) u32 *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (unlikely(!drv_ctx)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) spin_lock(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* Read again to check if some other core init drv_ctx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) drv_ctx = ctx->drv_ctx[type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (!drv_ctx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (type == ENCRYPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) desc = ctx->sh_desc_enc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) else /* (type == DECRYPT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) desc = ctx->sh_desc_dec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) drv_ctx = caam_drv_ctx_init(ctx->qidev, &cpu, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (!IS_ERR_OR_NULL(drv_ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) drv_ctx->op_type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ctx->drv_ctx[type] = drv_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) spin_unlock(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return drv_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static void caam_unmap(struct device *dev, struct scatterlist *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct scatterlist *dst, int src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int dst_nents, dma_addr_t iv_dma, int ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) enum dma_data_direction iv_dir, dma_addr_t qm_sg_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) int qm_sg_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (dst != src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (src_nents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (dst_nents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (iv_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dma_unmap_single(dev, iv_dma, ivsize, iv_dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (qm_sg_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) dma_unmap_single(dev, qm_sg_dma, qm_sg_bytes, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static void aead_unmap(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct aead_edesc *edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct crypto_aead *aead = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) int ivsize = crypto_aead_ivsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) caam_unmap(dev, req->src, req->dst, edesc->src_nents, edesc->dst_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) edesc->iv_dma, ivsize, DMA_TO_DEVICE, edesc->qm_sg_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) edesc->qm_sg_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dma_unmap_single(dev, edesc->assoclen_dma, 4, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static void skcipher_unmap(struct device *dev, struct skcipher_edesc *edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) int ivsize = crypto_skcipher_ivsize(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) caam_unmap(dev, req->src, req->dst, edesc->src_nents, edesc->dst_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) edesc->iv_dma, ivsize, DMA_BIDIRECTIONAL, edesc->qm_sg_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) edesc->qm_sg_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static void aead_done(struct caam_drv_req *drv_req, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct device *qidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct aead_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct aead_request *aead_req = drv_req->app_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct crypto_aead *aead = crypto_aead_reqtfm(aead_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct caam_ctx *caam_ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int ecode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) qidev = caam_ctx->qidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (unlikely(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ecode = caam_jr_strstatus(qidev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) edesc = container_of(drv_req, typeof(*edesc), drv_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) aead_unmap(qidev, edesc, aead_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) aead_request_complete(aead_req, ecode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * allocate and map the aead extended descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) bool encrypt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct crypto_aead *aead = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct caam_aead_alg *alg = container_of(crypto_aead_alg(aead),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) typeof(*alg), aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct device *qidev = ctx->qidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) GFP_KERNEL : GFP_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) int src_len, dst_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct aead_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dma_addr_t qm_sg_dma, iv_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) int ivsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) unsigned int authsize = ctx->authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) int qm_sg_index = 0, qm_sg_ents = 0, qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) int in_len, out_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct qm_sg_entry *sg_table, *fd_sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct caam_drv_ctx *drv_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) drv_ctx = get_drv_ctx(ctx, encrypt ? ENCRYPT : DECRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (IS_ERR_OR_NULL(drv_ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return (struct aead_edesc *)drv_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* allocate space for base edesc and hw desc commands, link tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) edesc = qi_cache_alloc(GFP_DMA | flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (unlikely(!edesc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dev_err(qidev, "could not allocate extended descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (likely(req->src == req->dst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) src_len = req->assoclen + req->cryptlen +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) (encrypt ? authsize : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) src_nents = sg_nents_for_len(req->src, src_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (unlikely(src_nents < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) dev_err(qidev, "Insufficient bytes (%d) in src S/G\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) src_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return ERR_PTR(src_nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) mapped_src_nents = dma_map_sg(qidev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (unlikely(!mapped_src_nents)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) dev_err(qidev, "unable to map source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) src_len = req->assoclen + req->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) dst_len = src_len + (encrypt ? authsize : (-authsize));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) src_nents = sg_nents_for_len(req->src, src_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (unlikely(src_nents < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) dev_err(qidev, "Insufficient bytes (%d) in src S/G\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) src_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return ERR_PTR(src_nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dst_nents = sg_nents_for_len(req->dst, dst_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (unlikely(dst_nents < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) dev_err(qidev, "Insufficient bytes (%d) in dst S/G\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) dst_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return ERR_PTR(dst_nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (src_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) mapped_src_nents = dma_map_sg(qidev, req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) src_nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (unlikely(!mapped_src_nents)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) dev_err(qidev, "unable to map source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) mapped_src_nents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (dst_nents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) mapped_dst_nents = dma_map_sg(qidev, req->dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) dst_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (unlikely(!mapped_dst_nents)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dev_err(qidev, "unable to map destination\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) dma_unmap_sg(qidev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) mapped_dst_nents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if ((alg->caam.rfc3686 && encrypt) || !alg->caam.geniv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) ivsize = crypto_aead_ivsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * Create S/G table: req->assoclen, [IV,] req->src [, req->dst].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) * Input is not contiguous.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * HW reads 4 S/G entries at a time; make sure the reads don't go beyond
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * the end of the table by allocating more S/G entries. Logic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * if (src != dst && output S/G)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * pad output S/G, if needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) * else if (src == dst && S/G)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) * overlapping S/Gs; pad one of them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) * else if (input S/G) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) * pad input S/G, if needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) qm_sg_ents = 1 + !!ivsize + mapped_src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (mapped_dst_nents > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) qm_sg_ents += pad_sg_nents(mapped_dst_nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) else if ((req->src == req->dst) && (mapped_src_nents > 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) qm_sg_ents = max(pad_sg_nents(qm_sg_ents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) 1 + !!ivsize + pad_sg_nents(mapped_src_nents));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) qm_sg_ents = pad_sg_nents(qm_sg_ents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) sg_table = &edesc->sgt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) qm_sg_bytes = qm_sg_ents * sizeof(*sg_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (unlikely(offsetof(struct aead_edesc, sgt) + qm_sg_bytes + ivsize >
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) CAAM_QI_MEMCACHE_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) dev_err(qidev, "No space for %d S/G entries and/or %dB IV\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) qm_sg_ents, ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) 0, DMA_NONE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (ivsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) u8 *iv = (u8 *)(sg_table + qm_sg_ents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* Make sure IV is located in a DMAable area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) memcpy(iv, req->iv, ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) iv_dma = dma_map_single(qidev, iv, ivsize, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (dma_mapping_error(qidev, iv_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) dev_err(qidev, "unable to map IV\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) caam_unmap(qidev, req->src, req->dst, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) dst_nents, 0, 0, DMA_NONE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) edesc->src_nents = src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) edesc->dst_nents = dst_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) edesc->iv_dma = iv_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) edesc->drv_req.app_ctx = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) edesc->drv_req.cbk = aead_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) edesc->drv_req.drv_ctx = drv_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) edesc->assoclen = cpu_to_caam32(req->assoclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) edesc->assoclen_dma = dma_map_single(qidev, &edesc->assoclen, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (dma_mapping_error(qidev, edesc->assoclen_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) dev_err(qidev, "unable to map assoclen\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) iv_dma, ivsize, DMA_TO_DEVICE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) dma_to_qm_sg_one(sg_table, edesc->assoclen_dma, 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) qm_sg_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (ivsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) dma_to_qm_sg_one(sg_table + qm_sg_index, iv_dma, ivsize, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) qm_sg_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) sg_to_qm_sg_last(req->src, src_len, sg_table + qm_sg_index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) qm_sg_index += mapped_src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (mapped_dst_nents > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) sg_to_qm_sg_last(req->dst, dst_len, sg_table + qm_sg_index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) qm_sg_dma = dma_map_single(qidev, sg_table, qm_sg_bytes, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (dma_mapping_error(qidev, qm_sg_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) dev_err(qidev, "unable to map S/G table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) dma_unmap_single(qidev, edesc->assoclen_dma, 4, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) iv_dma, ivsize, DMA_TO_DEVICE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) edesc->qm_sg_dma = qm_sg_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) edesc->qm_sg_bytes = qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) out_len = req->assoclen + req->cryptlen +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) (encrypt ? ctx->authsize : (-ctx->authsize));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) in_len = 4 + ivsize + req->assoclen + req->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) fd_sgt = &edesc->drv_req.fd_sgt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) dma_to_qm_sg_one_last_ext(&fd_sgt[1], qm_sg_dma, in_len, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (req->dst == req->src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (mapped_src_nents == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) dma_to_qm_sg_one(&fd_sgt[0], sg_dma_address(req->src),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) out_len, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dma_to_qm_sg_one_ext(&fd_sgt[0], qm_sg_dma +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) (1 + !!ivsize) * sizeof(*sg_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) out_len, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) } else if (mapped_dst_nents <= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) dma_to_qm_sg_one(&fd_sgt[0], sg_dma_address(req->dst), out_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) dma_to_qm_sg_one_ext(&fd_sgt[0], qm_sg_dma + sizeof(*sg_table) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) qm_sg_index, out_len, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static inline int aead_crypt(struct aead_request *req, bool encrypt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct aead_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct crypto_aead *aead = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct caam_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (unlikely(caam_congested))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* allocate extended descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) edesc = aead_edesc_alloc(req, encrypt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (IS_ERR_OR_NULL(edesc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return PTR_ERR(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* Create and submit job descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ret = caam_qi_enqueue(ctx->qidev, &edesc->drv_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ret = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) aead_unmap(ctx->qidev, edesc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static int aead_encrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return aead_crypt(req, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static int aead_decrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return aead_crypt(req, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static int ipsec_gcm_encrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return crypto_ipsec_check_assoclen(req->assoclen) ? : aead_crypt(req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static int ipsec_gcm_decrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return crypto_ipsec_check_assoclen(req->assoclen) ? : aead_crypt(req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static void skcipher_done(struct caam_drv_req *drv_req, u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) struct skcipher_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct skcipher_request *req = drv_req->app_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct caam_ctx *caam_ctx = crypto_skcipher_ctx(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) struct device *qidev = caam_ctx->qidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) int ivsize = crypto_skcipher_ivsize(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) int ecode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) dev_dbg(qidev, "%s %d: status 0x%x\n", __func__, __LINE__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) edesc = container_of(drv_req, typeof(*edesc), drv_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) ecode = caam_jr_strstatus(qidev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) print_hex_dump_debug("dstiv @" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) edesc->src_nents > 1 ? 100 : ivsize, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) caam_dump_sg("dst @" __stringify(__LINE__)": ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) DUMP_PREFIX_ADDRESS, 16, 4, req->dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) edesc->dst_nents > 1 ? 100 : req->cryptlen, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) skcipher_unmap(qidev, edesc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * The crypto API expects us to set the IV (req->iv) to the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * ciphertext block (CBC mode) or last counter (CTR mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * This is used e.g. by the CTS mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (!ecode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) memcpy(req->iv, (u8 *)&edesc->sgt[0] + edesc->qm_sg_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) skcipher_request_complete(req, ecode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static struct skcipher_edesc *skcipher_edesc_alloc(struct skcipher_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) bool encrypt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) struct device *qidev = ctx->qidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) gfp_t flags = (req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) GFP_KERNEL : GFP_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) int src_nents, mapped_src_nents, dst_nents = 0, mapped_dst_nents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) struct skcipher_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) dma_addr_t iv_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) u8 *iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) int ivsize = crypto_skcipher_ivsize(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) int dst_sg_idx, qm_sg_ents, qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct qm_sg_entry *sg_table, *fd_sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct caam_drv_ctx *drv_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) drv_ctx = get_drv_ctx(ctx, encrypt ? ENCRYPT : DECRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (IS_ERR_OR_NULL(drv_ctx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) return (struct skcipher_edesc *)drv_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) src_nents = sg_nents_for_len(req->src, req->cryptlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (unlikely(src_nents < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) dev_err(qidev, "Insufficient bytes (%d) in src S/G\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) req->cryptlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return ERR_PTR(src_nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (unlikely(req->src != req->dst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) dst_nents = sg_nents_for_len(req->dst, req->cryptlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (unlikely(dst_nents < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) dev_err(qidev, "Insufficient bytes (%d) in dst S/G\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) req->cryptlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return ERR_PTR(dst_nents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) mapped_src_nents = dma_map_sg(qidev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (unlikely(!mapped_src_nents)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) dev_err(qidev, "unable to map source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) mapped_dst_nents = dma_map_sg(qidev, req->dst, dst_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (unlikely(!mapped_dst_nents)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dev_err(qidev, "unable to map destination\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) dma_unmap_sg(qidev, req->src, src_nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) mapped_src_nents = dma_map_sg(qidev, req->src, src_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (unlikely(!mapped_src_nents)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) dev_err(qidev, "unable to map source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) qm_sg_ents = 1 + mapped_src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) dst_sg_idx = qm_sg_ents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) * Input, output HW S/G tables: [IV, src][dst, IV]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * IV entries point to the same buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * If src == dst, S/G entries are reused (S/G tables overlap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * HW reads 4 S/G entries at a time; make sure the reads don't go beyond
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * the end of the table by allocating more S/G entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (req->src != req->dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) qm_sg_ents += pad_sg_nents(mapped_dst_nents + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) qm_sg_ents = 1 + pad_sg_nents(qm_sg_ents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) qm_sg_bytes = qm_sg_ents * sizeof(struct qm_sg_entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (unlikely(offsetof(struct skcipher_edesc, sgt) + qm_sg_bytes +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) ivsize > CAAM_QI_MEMCACHE_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) dev_err(qidev, "No space for %d S/G entries and/or %dB IV\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) qm_sg_ents, ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) 0, DMA_NONE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) /* allocate space for base edesc, link tables and IV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) edesc = qi_cache_alloc(GFP_DMA | flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (unlikely(!edesc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dev_err(qidev, "could not allocate extended descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) 0, DMA_NONE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /* Make sure IV is located in a DMAable area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) sg_table = &edesc->sgt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) iv = (u8 *)(sg_table + qm_sg_ents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) memcpy(iv, req->iv, ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) iv_dma = dma_map_single(qidev, iv, ivsize, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (dma_mapping_error(qidev, iv_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) dev_err(qidev, "unable to map IV\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) 0, DMA_NONE, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) edesc->src_nents = src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) edesc->dst_nents = dst_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) edesc->iv_dma = iv_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) edesc->qm_sg_bytes = qm_sg_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) edesc->drv_req.app_ctx = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) edesc->drv_req.cbk = skcipher_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) edesc->drv_req.drv_ctx = drv_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) dma_to_qm_sg_one(sg_table, iv_dma, ivsize, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) sg_to_qm_sg(req->src, req->cryptlen, sg_table + 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (req->src != req->dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) sg_to_qm_sg(req->dst, req->cryptlen, sg_table + dst_sg_idx, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) dma_to_qm_sg_one(sg_table + dst_sg_idx + mapped_dst_nents, iv_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) ivsize, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) edesc->qm_sg_dma = dma_map_single(qidev, sg_table, edesc->qm_sg_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (dma_mapping_error(qidev, edesc->qm_sg_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dev_err(qidev, "unable to map S/G table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) caam_unmap(qidev, req->src, req->dst, src_nents, dst_nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) iv_dma, ivsize, DMA_BIDIRECTIONAL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) fd_sgt = &edesc->drv_req.fd_sgt[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) dma_to_qm_sg_one_last_ext(&fd_sgt[1], edesc->qm_sg_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ivsize + req->cryptlen, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (req->src == req->dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) dma_to_qm_sg_one_ext(&fd_sgt[0], edesc->qm_sg_dma +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) sizeof(*sg_table), req->cryptlen + ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) dma_to_qm_sg_one_ext(&fd_sgt[0], edesc->qm_sg_dma + dst_sg_idx *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) sizeof(*sg_table), req->cryptlen + ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) return edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static inline bool xts_skcipher_ivsize(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) unsigned int ivsize = crypto_skcipher_ivsize(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return !!get_unaligned((u64 *)(req->iv + (ivsize / 2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static inline int skcipher_crypt(struct skcipher_request *req, bool encrypt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct skcipher_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctx->jrdev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) * XTS is expected to return an error even for input length = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) * Note that the case input length < block size will be caught during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) * HW offloading and return an error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (!req->cryptlen && !ctx->fallback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (ctx->fallback && ((ctrlpriv->era <= 8 && xts_skcipher_ivsize(req)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) ctx->xts_key_fallback)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) struct caam_skcipher_req_ctx *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) skcipher_request_set_callback(&rctx->fallback_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) req->base.flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) req->base.complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) req->base.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) skcipher_request_set_crypt(&rctx->fallback_req, req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) req->dst, req->cryptlen, req->iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) return encrypt ? crypto_skcipher_encrypt(&rctx->fallback_req) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) crypto_skcipher_decrypt(&rctx->fallback_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (unlikely(caam_congested))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /* allocate extended descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) edesc = skcipher_edesc_alloc(req, encrypt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) if (IS_ERR(edesc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) return PTR_ERR(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) ret = caam_qi_enqueue(ctx->qidev, &edesc->drv_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) ret = -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) skcipher_unmap(ctx->qidev, edesc, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) qi_cache_free(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static int skcipher_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return skcipher_crypt(req, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static int skcipher_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return skcipher_crypt(req, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static struct caam_skcipher_alg driver_algs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .cra_name = "cbc(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .cra_driver_name = "cbc-aes-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .setkey = aes_skcipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .encrypt = skcipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .decrypt = skcipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .cra_name = "cbc(des3_ede)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .cra_driver_name = "cbc-3des-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .setkey = des3_skcipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .encrypt = skcipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .decrypt = skcipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .min_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .max_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .caam.class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .cra_name = "cbc(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .cra_driver_name = "cbc-des-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .setkey = des_skcipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .encrypt = skcipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .decrypt = skcipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .min_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .max_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .caam.class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .cra_name = "ctr(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .cra_driver_name = "ctr-aes-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .setkey = ctr_skcipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .encrypt = skcipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .decrypt = skcipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .chunksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .caam.class1_alg_type = OP_ALG_ALGSEL_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) OP_ALG_AAI_CTR_MOD128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .cra_name = "rfc3686(ctr(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .cra_driver_name = "rfc3686-ctr-aes-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .setkey = rfc3686_skcipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .encrypt = skcipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .decrypt = skcipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .min_keysize = AES_MIN_KEY_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) CTR_RFC3686_NONCE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .max_keysize = AES_MAX_KEY_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) CTR_RFC3686_NONCE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .ivsize = CTR_RFC3686_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .chunksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .class1_alg_type = OP_ALG_ALGSEL_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) OP_ALG_AAI_CTR_MOD128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .rfc3686 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .cra_name = "xts(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .cra_driver_name = "xts-aes-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .cra_flags = CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .setkey = xts_skcipher_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .encrypt = skcipher_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .decrypt = skcipher_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .min_keysize = 2 * AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .max_keysize = 2 * AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .caam.class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_XTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) static struct caam_aead_alg driver_aeads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .cra_name = "rfc4106(gcm(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .cra_driver_name = "rfc4106-gcm-aes-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .setkey = rfc4106_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .setauthsize = rfc4106_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .encrypt = ipsec_gcm_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .decrypt = ipsec_gcm_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .ivsize = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .nodkp = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .cra_name = "rfc4543(gcm(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .cra_driver_name = "rfc4543-gcm-aes-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .setkey = rfc4543_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .setauthsize = rfc4543_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .encrypt = ipsec_gcm_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .decrypt = ipsec_gcm_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .ivsize = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .nodkp = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) /* Galois Counter Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .cra_name = "gcm(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .cra_driver_name = "gcm-aes-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .setkey = gcm_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .setauthsize = gcm_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .ivsize = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .nodkp = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) /* single-pass ipsec_esp descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .cra_name = "authenc(hmac(md5),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .cra_driver_name = "authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) "cbc-aes-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .class2_alg_type = OP_ALG_ALGSEL_MD5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .cra_name = "echainiv(authenc(hmac(md5),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) "cbc(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .cra_driver_name = "echainiv-authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) "cbc-aes-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .class2_alg_type = OP_ALG_ALGSEL_MD5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .cra_name = "authenc(hmac(sha1),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .cra_driver_name = "authenc-hmac-sha1-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) "cbc-aes-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .cra_name = "echainiv(authenc(hmac(sha1),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) "cbc(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) "hmac-sha1-cbc-aes-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .cra_name = "authenc(hmac(sha224),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .cra_driver_name = "authenc-hmac-sha224-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) "cbc-aes-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) .cra_name = "echainiv(authenc(hmac(sha224),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) "cbc(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) "hmac-sha224-cbc-aes-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .cra_name = "authenc(hmac(sha256),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .cra_driver_name = "authenc-hmac-sha256-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) "cbc-aes-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .cra_name = "echainiv(authenc(hmac(sha256),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) "cbc(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) "hmac-sha256-cbc-aes-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) "caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .cra_name = "authenc(hmac(sha384),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .cra_driver_name = "authenc-hmac-sha384-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) "cbc-aes-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .maxauthsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .cra_name = "echainiv(authenc(hmac(sha384),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) "cbc(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) "hmac-sha384-cbc-aes-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) "caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .maxauthsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .cra_name = "authenc(hmac(sha512),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .cra_driver_name = "authenc-hmac-sha512-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) "cbc-aes-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .maxauthsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .cra_name = "echainiv(authenc(hmac(sha512),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) "cbc(aes)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) "hmac-sha512-cbc-aes-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) "caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .maxauthsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .cra_driver_name = "authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) "cbc-des3_ede-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .class2_alg_type = OP_ALG_ALGSEL_MD5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .cra_name = "echainiv(authenc(hmac(md5),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) "cbc(des3_ede)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .cra_driver_name = "echainiv-authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) "cbc-des3_ede-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .class2_alg_type = OP_ALG_ALGSEL_MD5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .cra_name = "authenc(hmac(sha1),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) .cra_driver_name = "authenc-hmac-sha1-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) "cbc-des3_ede-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .cra_name = "echainiv(authenc(hmac(sha1),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) "cbc(des3_ede)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) "hmac-sha1-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) "cbc-des3_ede-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .cra_name = "authenc(hmac(sha224),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .cra_driver_name = "authenc-hmac-sha224-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) "cbc-des3_ede-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .cra_name = "echainiv(authenc(hmac(sha224),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) "cbc(des3_ede)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) "hmac-sha224-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) "cbc-des3_ede-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .cra_name = "authenc(hmac(sha256),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .cra_driver_name = "authenc-hmac-sha256-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) "cbc-des3_ede-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .cra_name = "echainiv(authenc(hmac(sha256),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) "cbc(des3_ede)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) "hmac-sha256-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) "cbc-des3_ede-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .cra_name = "authenc(hmac(sha384),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .cra_driver_name = "authenc-hmac-sha384-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) "cbc-des3_ede-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .maxauthsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .cra_name = "echainiv(authenc(hmac(sha384),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) "cbc(des3_ede)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) "hmac-sha384-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) "cbc-des3_ede-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .maxauthsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .cra_name = "authenc(hmac(sha512),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .cra_driver_name = "authenc-hmac-sha512-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) "cbc-des3_ede-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .maxauthsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .cra_name = "echainiv(authenc(hmac(sha512),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) "cbc(des3_ede)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) "hmac-sha512-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) "cbc-des3_ede-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .setkey = des3_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) .maxauthsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .cra_name = "authenc(hmac(md5),cbc(des))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .cra_driver_name = "authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) "cbc-des-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .class2_alg_type = OP_ALG_ALGSEL_MD5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .cra_name = "echainiv(authenc(hmac(md5),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) "cbc(des)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .cra_driver_name = "echainiv-authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) "cbc-des-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .class2_alg_type = OP_ALG_ALGSEL_MD5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) .cra_name = "authenc(hmac(sha1),cbc(des))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) .cra_driver_name = "authenc-hmac-sha1-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) "cbc-des-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .cra_name = "echainiv(authenc(hmac(sha1),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) "cbc(des)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) "hmac-sha1-cbc-des-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .class2_alg_type = OP_ALG_ALGSEL_SHA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .cra_name = "authenc(hmac(sha224),cbc(des))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .cra_driver_name = "authenc-hmac-sha224-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) "cbc-des-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .cra_name = "echainiv(authenc(hmac(sha224),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) "cbc(des)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) "hmac-sha224-cbc-des-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) "caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .cra_name = "authenc(hmac(sha256),cbc(des))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .cra_driver_name = "authenc-hmac-sha256-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) "cbc-des-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .cra_name = "echainiv(authenc(hmac(sha256),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) "cbc(des)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) "hmac-sha256-cbc-des-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) "caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .cra_name = "authenc(hmac(sha384),cbc(des))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .cra_driver_name = "authenc-hmac-sha384-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) "cbc-des-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .maxauthsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .cra_name = "echainiv(authenc(hmac(sha384),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) "cbc(des)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) "hmac-sha384-cbc-des-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) "caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .maxauthsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .cra_name = "authenc(hmac(sha512),cbc(des))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .cra_driver_name = "authenc-hmac-sha512-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) "cbc-des-caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .maxauthsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) .aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) .cra_name = "echainiv(authenc(hmac(sha512),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) "cbc(des)))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .cra_driver_name = "echainiv-authenc-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) "hmac-sha512-cbc-des-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) "caam-qi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .setkey = aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) .setauthsize = aead_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .encrypt = aead_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .decrypt = aead_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) .maxauthsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .caam = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) OP_ALG_AAI_HMAC_PRECOMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .geniv = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) static int caam_init_common(struct caam_ctx *ctx, struct caam_alg_entry *caam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) bool uses_dkp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) struct caam_drv_private *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) * distribute tfms across job rings to ensure in-order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) * crypto request processing per tfm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) ctx->jrdev = caam_jr_alloc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) if (IS_ERR(ctx->jrdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) pr_err("Job Ring Device allocation for transform failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) return PTR_ERR(ctx->jrdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) dev = ctx->jrdev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) if (priv->era >= 6 && uses_dkp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) ctx->dir = DMA_BIDIRECTIONAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) ctx->dir = DMA_TO_DEVICE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) ctx->key_dma = dma_map_single(dev, ctx->key, sizeof(ctx->key),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) if (dma_mapping_error(dev, ctx->key_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) dev_err(dev, "unable to map key\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) caam_jr_free(ctx->jrdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) /* copy descriptor header template value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) ctx->cdata.algtype = OP_TYPE_CLASS1_ALG | caam->class1_alg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) ctx->adata.algtype = OP_TYPE_CLASS2_ALG | caam->class2_alg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) ctx->qidev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) spin_lock_init(&ctx->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) ctx->drv_ctx[ENCRYPT] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) ctx->drv_ctx[DECRYPT] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) static int caam_cra_init(struct crypto_skcipher *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) struct caam_skcipher_alg *caam_alg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) container_of(alg, typeof(*caam_alg), skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) struct caam_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) u32 alg_aai = caam_alg->caam.class1_alg_type & OP_ALG_AAI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) if (alg_aai == OP_ALG_AAI_XTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) const char *tfm_name = crypto_tfm_alg_name(&tfm->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) struct crypto_skcipher *fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) fallback = crypto_alloc_skcipher(tfm_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) CRYPTO_ALG_NEED_FALLBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) if (IS_ERR(fallback)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) pr_err("Failed to allocate %s fallback: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) tfm_name, PTR_ERR(fallback));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) return PTR_ERR(fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) ctx->fallback = fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) crypto_skcipher_set_reqsize(tfm, sizeof(struct caam_skcipher_req_ctx) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) crypto_skcipher_reqsize(fallback));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) ret = caam_init_common(ctx, &caam_alg->caam, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) if (ret && ctx->fallback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) crypto_free_skcipher(ctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) static int caam_aead_init(struct crypto_aead *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) struct aead_alg *alg = crypto_aead_alg(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) struct caam_aead_alg *caam_alg = container_of(alg, typeof(*caam_alg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) struct caam_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) return caam_init_common(ctx, &caam_alg->caam, !caam_alg->caam.nodkp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) static void caam_exit_common(struct caam_ctx *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) caam_drv_ctx_rel(ctx->drv_ctx[ENCRYPT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) caam_drv_ctx_rel(ctx->drv_ctx[DECRYPT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) dma_unmap_single(ctx->jrdev->parent, ctx->key_dma, sizeof(ctx->key),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) caam_jr_free(ctx->jrdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) static void caam_cra_exit(struct crypto_skcipher *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) struct caam_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) if (ctx->fallback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) crypto_free_skcipher(ctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) caam_exit_common(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) static void caam_aead_exit(struct crypto_aead *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) caam_exit_common(crypto_aead_ctx(tfm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) void caam_qi_algapi_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) struct caam_aead_alg *t_alg = driver_aeads + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) if (t_alg->registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) crypto_unregister_aead(&t_alg->aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) struct caam_skcipher_alg *t_alg = driver_algs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) if (t_alg->registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) crypto_unregister_skcipher(&t_alg->skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) static void caam_skcipher_alg_init(struct caam_skcipher_alg *t_alg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) struct skcipher_alg *alg = &t_alg->skcipher;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) alg->base.cra_module = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) alg->base.cra_priority = CAAM_CRA_PRIORITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) alg->base.cra_ctxsize = sizeof(struct caam_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) alg->base.cra_flags |= (CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) CRYPTO_ALG_KERN_DRIVER_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) alg->init = caam_cra_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) alg->exit = caam_cra_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) static void caam_aead_alg_init(struct caam_aead_alg *t_alg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) struct aead_alg *alg = &t_alg->aead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) alg->base.cra_module = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) alg->base.cra_priority = CAAM_CRA_PRIORITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) alg->base.cra_ctxsize = sizeof(struct caam_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) alg->base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_ALLOCATES_MEMORY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) CRYPTO_ALG_KERN_DRIVER_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) alg->init = caam_aead_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) alg->exit = caam_aead_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) int caam_qi_algapi_init(struct device *ctrldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) struct caam_drv_private *priv = dev_get_drvdata(ctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) int i = 0, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) u32 aes_vid, aes_inst, des_inst, md_vid, md_inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) unsigned int md_limit = SHA512_DIGEST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) bool registered = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) /* Make sure this runs only on (DPAA 1.x) QI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) if (!priv->qi_present || caam_dpaa2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) * Register crypto algorithms the device supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) * First, detect presence and attributes of DES, AES, and MD blocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) if (priv->era < 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) u32 cha_vid, cha_inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) aes_vid = cha_vid & CHA_ID_LS_AES_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) md_vid = (cha_vid & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) cha_inst = rd_reg32(&priv->ctrl->perfmon.cha_num_ls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) des_inst = (cha_inst & CHA_ID_LS_DES_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) CHA_ID_LS_DES_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) aes_inst = cha_inst & CHA_ID_LS_AES_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) md_inst = (cha_inst & CHA_ID_LS_MD_MASK) >> CHA_ID_LS_MD_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) u32 aesa, mdha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) aesa = rd_reg32(&priv->ctrl->vreg.aesa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) mdha = rd_reg32(&priv->ctrl->vreg.mdha);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) aes_vid = (aesa & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) md_vid = (mdha & CHA_VER_VID_MASK) >> CHA_VER_VID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) des_inst = rd_reg32(&priv->ctrl->vreg.desa) & CHA_VER_NUM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) aes_inst = aesa & CHA_VER_NUM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) md_inst = mdha & CHA_VER_NUM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) /* If MD is present, limit digest size based on LP256 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) if (md_inst && md_vid == CHA_VER_VID_MD_LP256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) md_limit = SHA256_DIGEST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) struct caam_skcipher_alg *t_alg = driver_algs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) u32 alg_sel = t_alg->caam.class1_alg_type & OP_ALG_ALGSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) /* Skip DES algorithms if not supported by device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) if (!des_inst &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) ((alg_sel == OP_ALG_ALGSEL_3DES) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) (alg_sel == OP_ALG_ALGSEL_DES)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) /* Skip AES algorithms if not supported by device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) if (!aes_inst && (alg_sel == OP_ALG_ALGSEL_AES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) caam_skcipher_alg_init(t_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) err = crypto_register_skcipher(&t_alg->skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) dev_warn(ctrldev, "%s alg registration failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) t_alg->skcipher.base.cra_driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) t_alg->registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) for (i = 0; i < ARRAY_SIZE(driver_aeads); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) struct caam_aead_alg *t_alg = driver_aeads + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) u32 c1_alg_sel = t_alg->caam.class1_alg_type &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) OP_ALG_ALGSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) u32 c2_alg_sel = t_alg->caam.class2_alg_type &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) OP_ALG_ALGSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) u32 alg_aai = t_alg->caam.class1_alg_type & OP_ALG_AAI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) /* Skip DES algorithms if not supported by device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) if (!des_inst &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) ((c1_alg_sel == OP_ALG_ALGSEL_3DES) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) (c1_alg_sel == OP_ALG_ALGSEL_DES)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) /* Skip AES algorithms if not supported by device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) if (!aes_inst && (c1_alg_sel == OP_ALG_ALGSEL_AES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) * Check support for AES algorithms not available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) * on LP devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) if (aes_vid == CHA_VER_VID_AES_LP && alg_aai == OP_ALG_AAI_GCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) * Skip algorithms requiring message digests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) * if MD or MD size is not supported by device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) if (c2_alg_sel &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) (!md_inst || (t_alg->aead.maxauthsize > md_limit)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) caam_aead_alg_init(t_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) err = crypto_register_aead(&t_alg->aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) pr_warn("%s alg registration failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) t_alg->aead.base.cra_driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) t_alg->registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) if (registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) dev_info(ctrldev, "algorithms registered in /proc/crypto\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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