^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cryptographic API.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Support for ATMEL DES/TDES HW acceleration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2012 Eukréa Electromatique - ATMEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Nicolas Royer <nicolas@eukrea.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Some ideas are from omap-aes.c drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/crypto.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <crypto/scatterwalk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <crypto/algapi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <crypto/internal/des.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <crypto/internal/skcipher.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "atmel-tdes-regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ATMEL_TDES_PRIORITY 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* TDES flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Reserve bits [17:16], [13:12], [2:0] for AES Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TDES_FLAGS_ENCRYPT TDES_MR_CYPHER_ENC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TDES_FLAGS_OPMODE_MASK (TDES_MR_OPMOD_MASK | TDES_MR_CFBS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TDES_FLAGS_ECB TDES_MR_OPMOD_ECB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TDES_FLAGS_CBC TDES_MR_OPMOD_CBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TDES_FLAGS_OFB TDES_MR_OPMOD_OFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TDES_FLAGS_CFB64 (TDES_MR_OPMOD_CFB | TDES_MR_CFBS_64b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TDES_FLAGS_CFB32 (TDES_MR_OPMOD_CFB | TDES_MR_CFBS_32b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TDES_FLAGS_CFB16 (TDES_MR_OPMOD_CFB | TDES_MR_CFBS_16b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TDES_FLAGS_CFB8 (TDES_MR_OPMOD_CFB | TDES_MR_CFBS_8b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TDES_FLAGS_MODE_MASK (TDES_FLAGS_OPMODE_MASK | TDES_FLAGS_ENCRYPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TDES_FLAGS_INIT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TDES_FLAGS_FAST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TDES_FLAGS_BUSY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TDES_FLAGS_DMA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ATMEL_TDES_QUEUE_LENGTH 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CFB8_BLOCK_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CFB16_BLOCK_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CFB32_BLOCK_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct atmel_tdes_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bool has_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 has_cfb_3keys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct atmel_tdes_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct atmel_tdes_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct atmel_tdes_dev *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 key[DES3_EDE_KEY_SIZE / sizeof(u32)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u16 block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct atmel_tdes_reqctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned long mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 lastc[DES_BLOCK_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct atmel_tdes_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct dma_slave_config dma_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct atmel_tdes_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct atmel_tdes_ctx *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct clk *iclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct crypto_queue queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct tasklet_struct done_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct tasklet_struct queue_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct skcipher_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) size_t total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct scatterlist *in_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int nb_in_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) size_t in_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct scatterlist *out_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int nb_out_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) size_t out_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) size_t buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) size_t dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void *buf_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int dma_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dma_addr_t dma_addr_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct atmel_tdes_dma dma_lch_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void *buf_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int dma_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dma_addr_t dma_addr_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct atmel_tdes_dma dma_lch_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct atmel_tdes_caps caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 hw_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct atmel_tdes_drv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct list_head dev_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct atmel_tdes_drv atmel_tdes = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .dev_list = LIST_HEAD_INIT(atmel_tdes.dev_list),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .lock = __SPIN_LOCK_UNLOCKED(atmel_tdes.lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int atmel_tdes_sg_copy(struct scatterlist **sg, size_t *offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void *buf, size_t buflen, size_t total, int out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) size_t count, off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) while (buflen && total) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) count = min((*sg)->length - *offset, total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) count = min(count, buflen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) scatterwalk_map_and_copy(buf + off, *sg, *offset, count, out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) off += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) buflen -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) *offset += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) total -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (*offset == (*sg)->length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *sg = sg_next(*sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (*sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) total = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static inline u32 atmel_tdes_read(struct atmel_tdes_dev *dd, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return readl_relaxed(dd->io_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static inline void atmel_tdes_write(struct atmel_tdes_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writel_relaxed(value, dd->io_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void atmel_tdes_write_n(struct atmel_tdes_dev *dd, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) const u32 *value, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) for (; count--; value++, offset += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) atmel_tdes_write(dd, offset, *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static struct atmel_tdes_dev *atmel_tdes_find_dev(struct atmel_tdes_ctx *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct atmel_tdes_dev *tdes_dd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct atmel_tdes_dev *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) spin_lock_bh(&atmel_tdes.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (!ctx->dd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) list_for_each_entry(tmp, &atmel_tdes.dev_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) tdes_dd = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ctx->dd = tdes_dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) tdes_dd = ctx->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) spin_unlock_bh(&atmel_tdes.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return tdes_dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static int atmel_tdes_hw_init(struct atmel_tdes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) err = clk_prepare_enable(dd->iclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!(dd->flags & TDES_FLAGS_INIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) atmel_tdes_write(dd, TDES_CR, TDES_CR_SWRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dd->flags |= TDES_FLAGS_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static inline unsigned int atmel_tdes_get_version(struct atmel_tdes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return atmel_tdes_read(dd, TDES_HW_VERSION) & 0x00000fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int atmel_tdes_hw_version_init(struct atmel_tdes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) err = atmel_tdes_hw_init(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dd->hw_version = atmel_tdes_get_version(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_info(dd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "version: 0x%x\n", dd->hw_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) clk_disable_unprepare(dd->iclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void atmel_tdes_dma_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct atmel_tdes_dev *dd = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* dma_lch_out - completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) tasklet_schedule(&dd->done_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int atmel_tdes_write_ctrl(struct atmel_tdes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 valmr = TDES_MR_SMOD_PDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) err = atmel_tdes_hw_init(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (!dd->caps.has_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) atmel_tdes_write(dd, TDES_PTCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) TDES_PTCR_TXTDIS | TDES_PTCR_RXTDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* MR register must be set before IV registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (dd->ctx->keylen > (DES_KEY_SIZE << 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) valmr |= TDES_MR_KEYMOD_3KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) valmr |= TDES_MR_TDESMOD_TDES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) } else if (dd->ctx->keylen > DES_KEY_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) valmr |= TDES_MR_KEYMOD_2KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) valmr |= TDES_MR_TDESMOD_TDES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) valmr |= TDES_MR_TDESMOD_DES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) valmr |= dd->flags & TDES_FLAGS_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) atmel_tdes_write(dd, TDES_MR, valmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) atmel_tdes_write_n(dd, TDES_KEY1W1R, dd->ctx->key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dd->ctx->keylen >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (dd->req->iv && (valmr & TDES_MR_OPMOD_MASK) != TDES_MR_OPMOD_ECB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) atmel_tdes_write_n(dd, TDES_IV1R, (void *)dd->req->iv, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int atmel_tdes_crypt_pdc_stop(struct atmel_tdes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) size_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (dd->flags & TDES_FLAGS_FAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dma_sync_single_for_device(dd->dev, dd->dma_addr_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dd->dma_size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* copy data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) count = atmel_tdes_sg_copy(&dd->out_sg, &dd->out_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dd->buf_out, dd->buflen, dd->dma_size, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (count != dd->dma_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) pr_err("not all data converted: %zu\n", count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int atmel_tdes_buff_init(struct atmel_tdes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dd->buf_in = (void *)__get_free_pages(GFP_KERNEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dd->buf_out = (void *)__get_free_pages(GFP_KERNEL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dd->buflen = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dd->buflen &= ~(DES_BLOCK_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (!dd->buf_in || !dd->buf_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_err(dd->dev, "unable to alloc pages.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) goto err_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* MAP here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dd->dma_addr_in = dma_map_single(dd->dev, dd->buf_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dd->buflen, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (dma_mapping_error(dd->dev, dd->dma_addr_in)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_err(dd->dev, "dma %zd bytes error\n", dd->buflen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) goto err_map_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dd->dma_addr_out = dma_map_single(dd->dev, dd->buf_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dd->buflen, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (dma_mapping_error(dd->dev, dd->dma_addr_out)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_err(dd->dev, "dma %zd bytes error\n", dd->buflen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) goto err_map_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) err_map_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) err_map_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) err_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) free_page((unsigned long)dd->buf_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) free_page((unsigned long)dd->buf_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pr_err("error: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void atmel_tdes_buff_cleanup(struct atmel_tdes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dma_unmap_single(dd->dev, dd->dma_addr_out, dd->buflen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) free_page((unsigned long)dd->buf_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) free_page((unsigned long)dd->buf_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int atmel_tdes_crypt_pdc(struct atmel_tdes_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dma_addr_t dma_addr_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dma_addr_t dma_addr_out, int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(dd->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int len32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dd->dma_size = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (!(dd->flags & TDES_FLAGS_FAST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dma_sync_single_for_device(dd->dev, dma_addr_in, length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) switch (rctx->mode & TDES_FLAGS_OPMODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case TDES_FLAGS_CFB8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) len32 = DIV_ROUND_UP(length, sizeof(u8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case TDES_FLAGS_CFB16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) len32 = DIV_ROUND_UP(length, sizeof(u16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) len32 = DIV_ROUND_UP(length, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) atmel_tdes_write(dd, TDES_TPR, dma_addr_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) atmel_tdes_write(dd, TDES_TCR, len32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) atmel_tdes_write(dd, TDES_RPR, dma_addr_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) atmel_tdes_write(dd, TDES_RCR, len32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Enable Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) atmel_tdes_write(dd, TDES_IER, TDES_INT_ENDRX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Start DMA transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTEN | TDES_PTCR_RXTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static int atmel_tdes_crypt_dma(struct atmel_tdes_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dma_addr_t dma_addr_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dma_addr_t dma_addr_out, int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(dd->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct scatterlist sg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct dma_async_tx_descriptor *in_desc, *out_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) enum dma_slave_buswidth addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dd->dma_size = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!(dd->flags & TDES_FLAGS_FAST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dma_sync_single_for_device(dd->dev, dma_addr_in, length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) switch (rctx->mode & TDES_FLAGS_OPMODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case TDES_FLAGS_CFB8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) case TDES_FLAGS_CFB16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dd->dma_lch_in.dma_conf.dst_addr_width = addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dd->dma_lch_out.dma_conf.src_addr_width = addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dmaengine_slave_config(dd->dma_lch_out.chan, &dd->dma_lch_out.dma_conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dd->flags |= TDES_FLAGS_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) sg_init_table(&sg[0], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) sg_dma_address(&sg[0]) = dma_addr_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) sg_dma_len(&sg[0]) = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) sg_init_table(&sg[1], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) sg_dma_address(&sg[1]) = dma_addr_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) sg_dma_len(&sg[1]) = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, &sg[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 1, DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (!in_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) out_desc = dmaengine_prep_slave_sg(dd->dma_lch_out.chan, &sg[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 1, DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!out_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) out_desc->callback = atmel_tdes_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) out_desc->callback_param = dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dmaengine_submit(out_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dma_async_issue_pending(dd->dma_lch_out.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dmaengine_submit(in_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dma_async_issue_pending(dd->dma_lch_in.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int atmel_tdes_crypt_start(struct atmel_tdes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int err, fast = 0, in, out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) size_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dma_addr_t addr_in, addr_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if ((!dd->in_offset) && (!dd->out_offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* check for alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) in = IS_ALIGNED((u32)dd->in_sg->offset, sizeof(u32)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) IS_ALIGNED(dd->in_sg->length, dd->ctx->block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) out = IS_ALIGNED((u32)dd->out_sg->offset, sizeof(u32)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) IS_ALIGNED(dd->out_sg->length, dd->ctx->block_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) fast = in && out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (sg_dma_len(dd->in_sg) != sg_dma_len(dd->out_sg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) fast = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (fast) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) count = min_t(size_t, dd->total, sg_dma_len(dd->in_sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) count = min_t(size_t, count, sg_dma_len(dd->out_sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) err = dma_map_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_err(dd->dev, "dma_map_sg() error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) err = dma_map_sg(dd->dev, dd->out_sg, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev_err(dd->dev, "dma_map_sg() error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dma_unmap_sg(dd->dev, dd->in_sg, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) addr_in = sg_dma_address(dd->in_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) addr_out = sg_dma_address(dd->out_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dd->flags |= TDES_FLAGS_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* use cache buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) count = atmel_tdes_sg_copy(&dd->in_sg, &dd->in_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dd->buf_in, dd->buflen, dd->total, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) addr_in = dd->dma_addr_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) addr_out = dd->dma_addr_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dd->flags &= ~TDES_FLAGS_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dd->total -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (dd->caps.has_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) err = atmel_tdes_crypt_dma(dd, addr_in, addr_out, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) err = atmel_tdes_crypt_pdc(dd, addr_in, addr_out, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (err && (dd->flags & TDES_FLAGS_FAST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) atmel_tdes_set_iv_as_last_ciphertext_block(struct atmel_tdes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct skcipher_request *req = dd->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned int ivsize = crypto_skcipher_ivsize(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (req->cryptlen < ivsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (rctx->mode & TDES_FLAGS_ENCRYPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) scatterwalk_map_and_copy(req->iv, req->dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) req->cryptlen - ivsize, ivsize, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (req->src == req->dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) memcpy(req->iv, rctx->lastc, ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) scatterwalk_map_and_copy(req->iv, req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) req->cryptlen - ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ivsize, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static void atmel_tdes_finish_req(struct atmel_tdes_dev *dd, int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct skcipher_request *req = dd->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) clk_disable_unprepare(dd->iclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dd->flags &= ~TDES_FLAGS_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (!err && (rctx->mode & TDES_FLAGS_OPMODE_MASK) != TDES_FLAGS_ECB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) atmel_tdes_set_iv_as_last_ciphertext_block(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) req->base.complete(&req->base, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int atmel_tdes_handle_queue(struct atmel_tdes_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct crypto_async_request *async_req, *backlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct atmel_tdes_ctx *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct atmel_tdes_reqctx *rctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int err, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) spin_lock_irqsave(&dd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = crypto_enqueue_request(&dd->queue, &req->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (dd->flags & TDES_FLAGS_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) spin_unlock_irqrestore(&dd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) backlog = crypto_get_backlog(&dd->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) async_req = crypto_dequeue_request(&dd->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (async_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dd->flags |= TDES_FLAGS_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) spin_unlock_irqrestore(&dd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!async_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (backlog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) backlog->complete(backlog, -EINPROGRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) req = skcipher_request_cast(async_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* assign new request to device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dd->req = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dd->total = req->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dd->in_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) dd->in_sg = req->src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dd->out_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dd->out_sg = req->dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) rctx->mode &= TDES_FLAGS_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dd->flags = (dd->flags & ~TDES_FLAGS_MODE_MASK) | rctx->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dd->ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ctx->dd = dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) err = atmel_tdes_write_ctrl(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) err = atmel_tdes_crypt_start(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* des_task will not finish it, so do it here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) atmel_tdes_finish_req(dd, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) tasklet_schedule(&dd->queue_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int atmel_tdes_crypt_dma_stop(struct atmel_tdes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) int err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) size_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (dd->flags & TDES_FLAGS_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (dd->flags & TDES_FLAGS_FAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) dma_sync_single_for_device(dd->dev, dd->dma_addr_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dd->dma_size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* copy data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) count = atmel_tdes_sg_copy(&dd->out_sg, &dd->out_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dd->buf_out, dd->buflen, dd->dma_size, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (count != dd->dma_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) pr_err("not all data converted: %zu\n", count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static int atmel_tdes_crypt(struct skcipher_request *req, unsigned long mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct atmel_tdes_ctx *ctx = crypto_skcipher_ctx(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct atmel_tdes_reqctx *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) switch (mode & TDES_FLAGS_OPMODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) case TDES_FLAGS_CFB8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (!IS_ALIGNED(req->cryptlen, CFB8_BLOCK_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) pr_err("request size is not exact amount of CFB8 blocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ctx->block_size = CFB8_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case TDES_FLAGS_CFB16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (!IS_ALIGNED(req->cryptlen, CFB16_BLOCK_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) pr_err("request size is not exact amount of CFB16 blocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ctx->block_size = CFB16_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) case TDES_FLAGS_CFB32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (!IS_ALIGNED(req->cryptlen, CFB32_BLOCK_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) pr_err("request size is not exact amount of CFB32 blocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ctx->block_size = CFB32_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (!IS_ALIGNED(req->cryptlen, DES_BLOCK_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) pr_err("request size is not exact amount of DES blocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ctx->block_size = DES_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) rctx->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if ((mode & TDES_FLAGS_OPMODE_MASK) != TDES_FLAGS_ECB &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) !(mode & TDES_FLAGS_ENCRYPT) && req->src == req->dst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) unsigned int ivsize = crypto_skcipher_ivsize(skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (req->cryptlen >= ivsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) scatterwalk_map_and_copy(rctx->lastc, req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) req->cryptlen - ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ivsize, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return atmel_tdes_handle_queue(ctx->dd, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static int atmel_tdes_dma_init(struct atmel_tdes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Try to grab 2 DMA channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dd->dma_lch_in.chan = dma_request_chan(dd->dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (IS_ERR(dd->dma_lch_in.chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ret = PTR_ERR(dd->dma_lch_in.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) goto err_dma_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) TDES_IDATA1R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) dd->dma_lch_in.dma_conf.src_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dd->dma_lch_in.dma_conf.src_addr_width =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dd->dma_lch_in.dma_conf.dst_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dd->dma_lch_in.dma_conf.dst_addr_width =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dd->dma_lch_in.dma_conf.device_fc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) dd->dma_lch_out.chan = dma_request_chan(dd->dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (IS_ERR(dd->dma_lch_out.chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ret = PTR_ERR(dd->dma_lch_out.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) goto err_dma_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) dd->dma_lch_out.dma_conf.src_addr = dd->phys_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) TDES_ODATA1R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dd->dma_lch_out.dma_conf.src_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) dd->dma_lch_out.dma_conf.src_addr_width =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dd->dma_lch_out.dma_conf.dst_maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) dd->dma_lch_out.dma_conf.dst_addr_width =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) dd->dma_lch_out.dma_conf.device_fc = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) err_dma_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dma_release_channel(dd->dma_lch_in.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) err_dma_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) dev_err(dd->dev, "no DMA channel available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static void atmel_tdes_dma_cleanup(struct atmel_tdes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dma_release_channel(dd->dma_lch_in.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dma_release_channel(dd->dma_lch_out.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int atmel_des_setkey(struct crypto_skcipher *tfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct atmel_tdes_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) err = verify_skcipher_des_key(tfm, key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) memcpy(ctx->key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ctx->keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static int atmel_tdes_setkey(struct crypto_skcipher *tfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct atmel_tdes_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) err = verify_skcipher_des3_key(tfm, key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) memcpy(ctx->key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ctx->keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static int atmel_tdes_ecb_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return atmel_tdes_crypt(req, TDES_FLAGS_ECB | TDES_FLAGS_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static int atmel_tdes_ecb_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return atmel_tdes_crypt(req, TDES_FLAGS_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int atmel_tdes_cbc_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return atmel_tdes_crypt(req, TDES_FLAGS_CBC | TDES_FLAGS_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static int atmel_tdes_cbc_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return atmel_tdes_crypt(req, TDES_FLAGS_CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static int atmel_tdes_cfb_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return atmel_tdes_crypt(req, TDES_FLAGS_CFB64 | TDES_FLAGS_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static int atmel_tdes_cfb_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return atmel_tdes_crypt(req, TDES_FLAGS_CFB64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static int atmel_tdes_cfb8_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return atmel_tdes_crypt(req, TDES_FLAGS_CFB8 | TDES_FLAGS_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int atmel_tdes_cfb8_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return atmel_tdes_crypt(req, TDES_FLAGS_CFB8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static int atmel_tdes_cfb16_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return atmel_tdes_crypt(req, TDES_FLAGS_CFB16 | TDES_FLAGS_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static int atmel_tdes_cfb16_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return atmel_tdes_crypt(req, TDES_FLAGS_CFB16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static int atmel_tdes_cfb32_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return atmel_tdes_crypt(req, TDES_FLAGS_CFB32 | TDES_FLAGS_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static int atmel_tdes_cfb32_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return atmel_tdes_crypt(req, TDES_FLAGS_CFB32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static int atmel_tdes_ofb_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return atmel_tdes_crypt(req, TDES_FLAGS_OFB | TDES_FLAGS_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static int atmel_tdes_ofb_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return atmel_tdes_crypt(req, TDES_FLAGS_OFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int atmel_tdes_init_tfm(struct crypto_skcipher *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct atmel_tdes_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct atmel_tdes_dev *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) crypto_skcipher_set_reqsize(tfm, sizeof(struct atmel_tdes_reqctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dd = atmel_tdes_find_dev(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (!dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static void atmel_tdes_skcipher_alg_init(struct skcipher_alg *alg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) alg->base.cra_priority = ATMEL_TDES_PRIORITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) alg->base.cra_flags = CRYPTO_ALG_ASYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) alg->base.cra_ctxsize = sizeof(struct atmel_tdes_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) alg->base.cra_module = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) alg->init = atmel_tdes_init_tfm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static struct skcipher_alg tdes_algs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .base.cra_name = "ecb(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .base.cra_driver_name = "atmel-ecb-des",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .base.cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .base.cra_alignmask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .min_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .max_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .setkey = atmel_des_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .encrypt = atmel_tdes_ecb_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .decrypt = atmel_tdes_ecb_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .base.cra_name = "cbc(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .base.cra_driver_name = "atmel-cbc-des",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .base.cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .base.cra_alignmask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .min_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .max_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .setkey = atmel_des_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .encrypt = atmel_tdes_cbc_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .decrypt = atmel_tdes_cbc_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .base.cra_name = "cfb(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .base.cra_driver_name = "atmel-cfb-des",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .base.cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .base.cra_alignmask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .min_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .max_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .setkey = atmel_des_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .encrypt = atmel_tdes_cfb_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .decrypt = atmel_tdes_cfb_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .base.cra_name = "cfb8(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .base.cra_driver_name = "atmel-cfb8-des",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .base.cra_blocksize = CFB8_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .base.cra_alignmask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .min_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .max_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .setkey = atmel_des_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .encrypt = atmel_tdes_cfb8_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .decrypt = atmel_tdes_cfb8_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .base.cra_name = "cfb16(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .base.cra_driver_name = "atmel-cfb16-des",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .base.cra_blocksize = CFB16_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .base.cra_alignmask = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .min_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .max_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .setkey = atmel_des_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .encrypt = atmel_tdes_cfb16_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .decrypt = atmel_tdes_cfb16_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .base.cra_name = "cfb32(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .base.cra_driver_name = "atmel-cfb32-des",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .base.cra_blocksize = CFB32_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .base.cra_alignmask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .min_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .max_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .setkey = atmel_des_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .encrypt = atmel_tdes_cfb32_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .decrypt = atmel_tdes_cfb32_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .base.cra_name = "ofb(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .base.cra_driver_name = "atmel-ofb-des",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .base.cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .base.cra_alignmask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .min_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .max_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .setkey = atmel_des_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .encrypt = atmel_tdes_ofb_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .decrypt = atmel_tdes_ofb_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .base.cra_name = "ecb(des3_ede)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .base.cra_driver_name = "atmel-ecb-tdes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .base.cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .base.cra_alignmask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .min_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .max_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .setkey = atmel_tdes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .encrypt = atmel_tdes_ecb_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .decrypt = atmel_tdes_ecb_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .base.cra_name = "cbc(des3_ede)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .base.cra_driver_name = "atmel-cbc-tdes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .base.cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .base.cra_alignmask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .min_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .max_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .setkey = atmel_tdes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .encrypt = atmel_tdes_cbc_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .decrypt = atmel_tdes_cbc_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .base.cra_name = "ofb(des3_ede)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .base.cra_driver_name = "atmel-ofb-tdes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .base.cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .base.cra_alignmask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .min_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .max_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .setkey = atmel_tdes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .encrypt = atmel_tdes_ofb_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .decrypt = atmel_tdes_ofb_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static void atmel_tdes_queue_task(unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct atmel_tdes_dev *dd = (struct atmel_tdes_dev *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) atmel_tdes_handle_queue(dd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static void atmel_tdes_done_task(unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct atmel_tdes_dev *dd = (struct atmel_tdes_dev *) data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (!(dd->flags & TDES_FLAGS_DMA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) err = atmel_tdes_crypt_pdc_stop(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) err = atmel_tdes_crypt_dma_stop(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (dd->total && !err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (dd->flags & TDES_FLAGS_FAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dd->in_sg = sg_next(dd->in_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) dd->out_sg = sg_next(dd->out_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (!dd->in_sg || !dd->out_sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) err = atmel_tdes_crypt_start(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return; /* DMA started. Not fininishing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) atmel_tdes_finish_req(dd, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) atmel_tdes_handle_queue(dd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static irqreturn_t atmel_tdes_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct atmel_tdes_dev *tdes_dd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) reg = atmel_tdes_read(tdes_dd, TDES_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (reg & atmel_tdes_read(tdes_dd, TDES_IMR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) atmel_tdes_write(tdes_dd, TDES_IDR, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (TDES_FLAGS_BUSY & tdes_dd->flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) tasklet_schedule(&tdes_dd->done_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) dev_warn(tdes_dd->dev, "TDES interrupt when no active requests.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static void atmel_tdes_unregister_algs(struct atmel_tdes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) for (i = 0; i < ARRAY_SIZE(tdes_algs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) crypto_unregister_skcipher(&tdes_algs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static int atmel_tdes_register_algs(struct atmel_tdes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) int err, i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) for (i = 0; i < ARRAY_SIZE(tdes_algs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) atmel_tdes_skcipher_alg_init(&tdes_algs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) err = crypto_register_skcipher(&tdes_algs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) goto err_tdes_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) err_tdes_algs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) for (j = 0; j < i; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) crypto_unregister_skcipher(&tdes_algs[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static void atmel_tdes_get_cap(struct atmel_tdes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) dd->caps.has_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dd->caps.has_cfb_3keys = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* keep only major version number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) switch (dd->hw_version & 0xf00) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) case 0x700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dd->caps.has_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) dd->caps.has_cfb_3keys = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) case 0x600:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dev_warn(dd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) "Unmanaged tdes version, set minimum capabilities\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #if defined(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static const struct of_device_id atmel_tdes_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) { .compatible = "atmel,at91sam9g46-tdes" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) MODULE_DEVICE_TABLE(of, atmel_tdes_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static int atmel_tdes_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) struct atmel_tdes_dev *tdes_dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct resource *tdes_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) tdes_dd = devm_kmalloc(&pdev->dev, sizeof(*tdes_dd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (!tdes_dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) tdes_dd->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) platform_set_drvdata(pdev, tdes_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) INIT_LIST_HEAD(&tdes_dd->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) spin_lock_init(&tdes_dd->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) tasklet_init(&tdes_dd->done_task, atmel_tdes_done_task,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) (unsigned long)tdes_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) tasklet_init(&tdes_dd->queue_task, atmel_tdes_queue_task,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) (unsigned long)tdes_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) crypto_init_queue(&tdes_dd->queue, ATMEL_TDES_QUEUE_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* Get the base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) tdes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (!tdes_res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) dev_err(dev, "no MEM resource info\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) goto err_tasklet_kill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) tdes_dd->phys_base = tdes_res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* Get the IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) tdes_dd->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (tdes_dd->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) err = tdes_dd->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) goto err_tasklet_kill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) err = devm_request_irq(&pdev->dev, tdes_dd->irq, atmel_tdes_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) IRQF_SHARED, "atmel-tdes", tdes_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) dev_err(dev, "unable to request tdes irq.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) goto err_tasklet_kill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) /* Initializing the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) tdes_dd->iclk = devm_clk_get(&pdev->dev, "tdes_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (IS_ERR(tdes_dd->iclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) dev_err(dev, "clock initialization failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) err = PTR_ERR(tdes_dd->iclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) goto err_tasklet_kill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) tdes_dd->io_base = devm_ioremap_resource(&pdev->dev, tdes_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (IS_ERR(tdes_dd->io_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) dev_err(dev, "can't ioremap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) err = PTR_ERR(tdes_dd->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) goto err_tasklet_kill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) err = atmel_tdes_hw_version_init(tdes_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) goto err_tasklet_kill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) atmel_tdes_get_cap(tdes_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) err = atmel_tdes_buff_init(tdes_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) goto err_tasklet_kill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (tdes_dd->caps.has_dma) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) err = atmel_tdes_dma_init(tdes_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) goto err_buff_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) dev_info(dev, "using %s, %s for DMA transfers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) dma_chan_name(tdes_dd->dma_lch_in.chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) dma_chan_name(tdes_dd->dma_lch_out.chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) spin_lock(&atmel_tdes.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) list_add_tail(&tdes_dd->list, &atmel_tdes.dev_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) spin_unlock(&atmel_tdes.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) err = atmel_tdes_register_algs(tdes_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) goto err_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) dev_info(dev, "Atmel DES/TDES\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) err_algs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) spin_lock(&atmel_tdes.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) list_del(&tdes_dd->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) spin_unlock(&atmel_tdes.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (tdes_dd->caps.has_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) atmel_tdes_dma_cleanup(tdes_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) err_buff_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) atmel_tdes_buff_cleanup(tdes_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) err_tasklet_kill:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) tasklet_kill(&tdes_dd->done_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) tasklet_kill(&tdes_dd->queue_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static int atmel_tdes_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) struct atmel_tdes_dev *tdes_dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) tdes_dd = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (!tdes_dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) spin_lock(&atmel_tdes.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) list_del(&tdes_dd->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) spin_unlock(&atmel_tdes.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) atmel_tdes_unregister_algs(tdes_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) tasklet_kill(&tdes_dd->done_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) tasklet_kill(&tdes_dd->queue_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (tdes_dd->caps.has_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) atmel_tdes_dma_cleanup(tdes_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) atmel_tdes_buff_cleanup(tdes_dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static struct platform_driver atmel_tdes_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .probe = atmel_tdes_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .remove = atmel_tdes_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .name = "atmel_tdes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .of_match_table = of_match_ptr(atmel_tdes_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) module_platform_driver(atmel_tdes_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) MODULE_DESCRIPTION("Atmel DES/TDES hw acceleration support.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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