^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ATMEL_AES_REGS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ATMEL_AES_REGS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define AES_CR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define AES_CR_START (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define AES_CR_SWRST (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define AES_CR_LOADSEED (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define AES_MR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define AES_MR_CYPHER_DEC (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define AES_MR_CYPHER_ENC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define AES_MR_GTAGEN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define AES_MR_DUALBUFF (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define AES_MR_PROCDLY_MASK (0xF << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AES_MR_PROCDLY_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AES_MR_SMOD_MASK (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define AES_MR_SMOD_MANUAL (0x0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define AES_MR_SMOD_AUTO (0x1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AES_MR_SMOD_IDATAR0 (0x2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AES_MR_KEYSIZE_MASK (0x3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AES_MR_KEYSIZE_128 (0x0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AES_MR_KEYSIZE_192 (0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AES_MR_KEYSIZE_256 (0x2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AES_MR_OPMOD_MASK (0x7 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AES_MR_OPMOD_ECB (0x0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define AES_MR_OPMOD_CBC (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AES_MR_OPMOD_OFB (0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AES_MR_OPMOD_CFB (0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AES_MR_OPMOD_CTR (0x4 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AES_MR_OPMOD_GCM (0x5 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AES_MR_OPMOD_XTS (0x6 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AES_MR_LOD (0x1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AES_MR_CFBS_MASK (0x7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define AES_MR_CFBS_128b (0x0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AES_MR_CFBS_64b (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AES_MR_CFBS_32b (0x2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AES_MR_CFBS_16b (0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AES_MR_CFBS_8b (0x4 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define AES_MR_CKEY_MASK (0xF << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AES_MR_CKEY_OFFSET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define AES_MR_CMTYP_MASK (0x1F << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AES_MR_CMTYP_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AES_IER 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AES_IDR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AES_IMR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AES_ISR 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AES_INT_DATARDY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AES_INT_URAD (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AES_INT_TAGRDY (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AES_ISR_URAT_MASK (0xF << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AES_ISR_URAT_IDR_WR_PROC (0x0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AES_ISR_URAT_ODR_RD_PROC (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AES_ISR_URAT_MR_WR_PROC (0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AES_ISR_URAT_ODR_RD_SUBK (0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AES_ISR_URAT_MR_WR_SUBK (0x4 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AES_ISR_URAT_WOR_RD (0x5 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AES_KEYWR(x) (0x20 + ((x) * 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AES_IDATAR(x) (0x40 + ((x) * 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define AES_ODATAR(x) (0x50 + ((x) * 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AES_IVR(x) (0x60 + ((x) * 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AES_AADLENR 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AES_CLENR 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define AES_GHASHR(x) (0x78 + ((x) * 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AES_TAGR(x) (0x88 + ((x) * 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AES_CTRR 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AES_GCMHR(x) (0x9c + ((x) * 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AES_EMR 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AES_EMR_APEN BIT(0) /* Auto Padding Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AES_EMR_APM BIT(1) /* Auto Padding Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AES_EMR_APM_IPSEC 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AES_EMR_APM_SSL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AES_EMR_PLIPEN BIT(4) /* PLIP Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AES_EMR_PLIPD BIT(5) /* PLIP Decipher */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AES_EMR_PADLEN_MASK (0xFu << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AES_EMR_PADLEN_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AES_EMR_PADLEN(padlen) (((padlen) << AES_EMR_PADLEN_OFFSET) &\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) AES_EMR_PADLEN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define AES_EMR_NHEAD_MASK (0xFu << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AES_EMR_NHEAD_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AES_EMR_NHEAD(nhead) (((nhead) << AES_EMR_NHEAD_OFFSET) &\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) AES_EMR_NHEAD_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AES_TWR(x) (0xc0 + ((x) * 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define AES_ALPHAR(x) (0xd0 + ((x) * 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AES_HW_VERSION 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #endif /* __ATMEL_AES_REGS_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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