^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * CPU idle driver for Tegra CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2010-2013, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2011 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Colin Cross <ccross@android.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Gary King <gking@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Tegra20/124 driver unification by Dmitry Osipenko <digetx@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define pr_fmt(fmt) "tegra-cpuidle: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/cpuidle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/clk/tegra.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/firmware/trusted_foundations.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <soc/tegra/cpuidle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <soc/tegra/flowctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <soc/tegra/fuse.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <soc/tegra/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <soc/tegra/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <soc/tegra/pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/cpuidle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum tegra_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) TEGRA_C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) TEGRA_C7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) TEGRA_CC6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) TEGRA_STATE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static atomic_t tegra_idle_barrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static atomic_t tegra_abort_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static inline bool tegra_cpuidle_using_firmware(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return firmware_ops->prepare_idle && firmware_ops->do_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void tegra_cpuidle_report_cpus_state(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned long cpu, lcpu, csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) for_each_cpu(lcpu, cpu_possible_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) cpu = cpu_logical_map(lcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) csr = flowctrl_read_cpu_csr(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) pr_err("cpu%lu: online=%d flowctrl_csr=0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) cpu, cpu_online(lcpu), csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int tegra_cpuidle_wait_for_secondary_cpus_parking(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int retries = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) while (retries--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int delay_us = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int timeout_us = 500 * 1000 / delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * The primary CPU0 core shall wait for the secondaries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * shutdown in order to power-off CPU's cluster safely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * The timeout value depends on the current CPU frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * it takes about 40-150us in average and over 1000us in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * a worst case scenario.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (tegra_cpu_rail_off_ready())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) udelay(delay_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) } while (timeout_us--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pr_err("secondary CPU taking too long to park\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) tegra_cpuidle_report_cpus_state();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pr_err("timed out waiting secondaries to park\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void tegra_cpuidle_unpark_secondary_cpus(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int cpu, lcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) for_each_cpu(lcpu, cpu_online_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) cpu = cpu_logical_map(lcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (cpu > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) tegra_enable_cpu_clock(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) tegra_cpu_out_of_reset(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) flowctrl_write_cpu_halt(cpu, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int tegra_cpuidle_cc6_enter(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (cpu > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ret = cpu_suspend(cpu, tegra_pm_park_secondary_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = tegra_cpuidle_wait_for_secondary_cpus_parking();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = tegra_pm_enter_lp2();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) tegra_cpuidle_unpark_secondary_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int tegra_cpuidle_c7_enter(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) err = call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (err && err != -ENOSYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) err = call_firmware_op(do_idle, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (err != -ENOSYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return cpu_suspend(0, tegra30_pm_secondary_cpu_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int tegra_cpuidle_coupled_barrier(struct cpuidle_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (tegra_pending_sgi()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * CPU got local interrupt that will be lost after GIC's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * shutdown because GIC driver doesn't save/restore the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * pending SGI state across CPU cluster PM. Abort and retry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * next time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) atomic_set(&tegra_abort_flag, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) cpuidle_coupled_parallel_barrier(dev, &tegra_idle_barrier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (atomic_read(&tegra_abort_flag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) cpuidle_coupled_parallel_barrier(dev, &tegra_idle_barrier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) atomic_set(&tegra_abort_flag, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -EINTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int tegra_cpuidle_state_enter(struct cpuidle_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int index, unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * CC6 state is the "CPU cluster power-off" state. In order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * enter this state, at first the secondary CPU cores need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * parked into offline mode, then the last CPU should clean out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * remaining dirty cache lines into DRAM and trigger Flow Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * logic that turns off the cluster's power domain (which includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * CPU cores, GIC and L2 cache).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (index == TEGRA_CC6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) err = tegra_cpuidle_coupled_barrier(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) local_fiq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) RCU_NONIDLE(tegra_pm_set_cpu_in_lp2());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) cpu_pm_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case TEGRA_C7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) err = tegra_cpuidle_c7_enter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case TEGRA_CC6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) err = tegra_cpuidle_cc6_enter(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) cpu_pm_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) RCU_NONIDLE(tegra_pm_clear_cpu_in_lp2());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) local_fiq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return err ?: index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int tegra_cpuidle_adjust_state_index(int index, unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * On Tegra30 CPU0 can't be power-gated separately from secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * cores because it gates the whole CPU cluster.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (cpu > 0 || index != TEGRA_C7 || tegra_get_chip_id() != TEGRA30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* put CPU0 into C1 if C7 is requested and secondaries are online */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!IS_ENABLED(CONFIG_PM_SLEEP) || num_online_cpus() > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) index = TEGRA_C1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) index = TEGRA_CC6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int tegra_cpuidle_enter(struct cpuidle_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct cpuidle_driver *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int cpu = cpu_logical_map(dev->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) index = tegra_cpuidle_adjust_state_index(index, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (dev->states_usage[index].disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (index == TEGRA_C1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret = arm_cpuidle_simple_enter(dev, drv, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = tegra_cpuidle_state_enter(dev, index, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (ret != -EINTR || index != TEGRA_CC6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pr_err_once("failed to enter state %d err: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) index, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) index = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) index = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int tegra114_enter_s2idle(struct cpuidle_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct cpuidle_driver *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) tegra_cpuidle_enter(dev, drv, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * The previous versions of Tegra CPUIDLE driver used a different "legacy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * terminology for naming of the idling states, while this driver uses the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * new terminology.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * Mapping of the old terms into the new ones:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Old | New
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * ---------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * LP3 | C1 (CPU core clock gating)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * LP2 | C7 (CPU core power gating)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * LP2 | CC6 (CPU cluster power gating)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Note that that the older CPUIDLE driver versions didn't explicitly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * differentiate the LP2 states because these states either used the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * code path or because CC6 wasn't supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct cpuidle_driver tegra_idle_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .name = "tegra_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .states = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) [TEGRA_C1] = ARM_CPUIDLE_WFI_STATE_PWR(600),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) [TEGRA_C7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .enter = tegra_cpuidle_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .exit_latency = 2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .target_residency = 2200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .power_usage = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .flags = CPUIDLE_FLAG_TIMER_STOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .name = "C7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .desc = "CPU core powered off",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [TEGRA_CC6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .enter = tegra_cpuidle_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .exit_latency = 5000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .target_residency = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .power_usage = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .flags = CPUIDLE_FLAG_TIMER_STOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) CPUIDLE_FLAG_COUPLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .name = "CC6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .desc = "CPU cluster powered off",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .state_count = TEGRA_STATE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .safe_state_index = TEGRA_C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static inline void tegra_cpuidle_disable_state(enum tegra_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) cpuidle_driver_state_disabled(&tegra_idle_driver, state, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * they are legacy IRQs or MSI, are lost when CC6 is enabled. To work around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * this, simply disable CC6 if the PCI driver and DT node are both enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) void tegra_cpuidle_pcie_irqs_in_use(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct cpuidle_state *state_cc6 = &tegra_idle_driver.states[TEGRA_CC6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if ((state_cc6->flags & CPUIDLE_FLAG_UNUSABLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) tegra_get_chip_id() != TEGRA20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pr_info("disabling CC6 state, since PCIe IRQs are in use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) tegra_cpuidle_disable_state(TEGRA_CC6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static void tegra_cpuidle_setup_tegra114_c7_state(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct cpuidle_state *s = &tegra_idle_driver.states[TEGRA_C7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) s->enter_s2idle = tegra114_enter_s2idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) s->target_residency = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) s->exit_latency = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int tegra_cpuidle_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* LP2 could be disabled in device-tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (tegra_pmc_get_suspend_mode() < TEGRA_SUSPEND_LP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) tegra_cpuidle_disable_state(TEGRA_CC6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * Required suspend-resume functionality, which is provided by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * Tegra-arch core and PMC driver, is unavailable if PM-sleep option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (!IS_ENABLED(CONFIG_PM_SLEEP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!tegra_cpuidle_using_firmware())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) tegra_cpuidle_disable_state(TEGRA_C7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) tegra_cpuidle_disable_state(TEGRA_CC6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * Generic WFI state (also known as C1 or LP3) and the coupled CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * cluster power-off (CC6 or LP2) states are common for all Tegra SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) switch (tegra_get_chip_id()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) case TEGRA20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Tegra20 isn't capable to power-off individual CPU cores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) tegra_cpuidle_disable_state(TEGRA_C7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case TEGRA30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) case TEGRA114:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case TEGRA124:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) tegra_cpuidle_setup_tegra114_c7_state();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* coupled CC6 (LP2) state isn't implemented yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) tegra_cpuidle_disable_state(TEGRA_CC6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static struct platform_driver tegra_cpuidle_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .probe = tegra_cpuidle_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .name = "tegra-cpuidle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) builtin_platform_driver(tegra_cpuidle_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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