Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (c) 2014,2015, Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * SAW power controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/cpuidle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/cpu_pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/qcom_scm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/proc-fns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "dt_idle_states.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MAX_PMIC_DATA		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MAX_SEQ_DATA		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SPM_CTL_INDEX		0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SPM_CTL_INDEX_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SPM_CTL_EN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) enum pm_sleep_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	PM_SLEEP_MODE_STBY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	PM_SLEEP_MODE_RET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	PM_SLEEP_MODE_SPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	PM_SLEEP_MODE_PC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	PM_SLEEP_MODE_NR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) enum spm_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	SPM_REG_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	SPM_REG_SPM_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	SPM_REG_DLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	SPM_REG_PMIC_DLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	SPM_REG_PMIC_DATA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	SPM_REG_PMIC_DATA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	SPM_REG_VCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	SPM_REG_SEQ_ENTRY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	SPM_REG_SPM_STS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	SPM_REG_PMIC_STS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	SPM_REG_NR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) struct spm_reg_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	const u8 *reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u32 spm_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u32 spm_dly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u32 pmic_dly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u32 pmic_data[MAX_PMIC_DATA];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u8 seq[MAX_SEQ_DATA];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u8 start_index[PM_SLEEP_MODE_NR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) struct spm_driver_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct cpuidle_driver cpuidle_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	const struct spm_reg_data *reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	[SPM_REG_CFG]		= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	[SPM_REG_SPM_CTL]	= 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	[SPM_REG_DLY]		= 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	[SPM_REG_SEQ_ENTRY]	= 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* SPM register data for 8974, 8084 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static const struct spm_reg_data spm_reg_8974_8084_cpu  = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.reg_offset = spm_reg_offset_v2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.spm_cfg = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.spm_dly = 0x3C102800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	.seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		0x0F },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.start_index[PM_SLEEP_MODE_STBY] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.start_index[PM_SLEEP_MODE_SPC] = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	[SPM_REG_CFG]		= 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	[SPM_REG_SPM_CTL]	= 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	[SPM_REG_PMIC_DLY]	= 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	[SPM_REG_PMIC_DATA_0]	= 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	[SPM_REG_PMIC_DATA_1]	= 0x2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	[SPM_REG_SEQ_ENTRY]	= 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /* SPM register data for 8064 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const struct spm_reg_data spm_reg_8064_cpu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.reg_offset = spm_reg_offset_v1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.spm_cfg = 0x1F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.pmic_dly = 0x02020004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.pmic_data[0] = 0x0084009C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.pmic_data[1] = 0x00A4001C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.start_index[PM_SLEEP_MODE_STBY] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.start_index[PM_SLEEP_MODE_SPC] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static inline void spm_register_write(struct spm_driver_data *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 					enum spm_reg reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	if (drv->reg_data->reg_offset[reg])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		writel_relaxed(val, drv->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 				drv->reg_data->reg_offset[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Ensure a guaranteed write, before return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static inline void spm_register_write_sync(struct spm_driver_data *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 					enum spm_reg reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (!drv->reg_data->reg_offset[reg])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		writel_relaxed(val, drv->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				drv->reg_data->reg_offset[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		ret = readl_relaxed(drv->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 				drv->reg_data->reg_offset[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		if (ret == val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	} while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static inline u32 spm_register_read(struct spm_driver_data *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 					enum spm_reg reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	return readl_relaxed(drv->reg_base + drv->reg_data->reg_offset[reg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void spm_set_low_power_mode(struct spm_driver_data *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 					enum pm_sleep_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	u32 start_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	u32 ctl_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	start_index = drv->reg_data->start_index[mode];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	ctl_val = spm_register_read(drv, SPM_REG_SPM_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	ctl_val &= ~(SPM_CTL_INDEX << SPM_CTL_INDEX_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	ctl_val |= start_index << SPM_CTL_INDEX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	ctl_val |= SPM_CTL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int qcom_pm_collapse(unsigned long int unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	qcom_scm_cpu_power_down(QCOM_SCM_CPU_PWR_DOWN_L2_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	 * Returns here only if there was a pending interrupt and we did not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	 * power down as a result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int qcom_cpu_spc(struct spm_driver_data *drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	spm_set_low_power_mode(drv, PM_SLEEP_MODE_SPC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	ret = cpu_suspend(0, qcom_pm_collapse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	 * ARM common code executes WFI without calling into our driver and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * if the SPM mode is not reset, then we may accidently power down the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 * cpu when we intended only to gate the cpu clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	 * Ensure the state is set to standby before returning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int spm_enter_idle_state(struct cpuidle_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				struct cpuidle_driver *drv, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct spm_driver_data *data = container_of(drv, struct spm_driver_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 						    cpuidle_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	return CPU_PM_CPU_IDLE_ENTER_PARAM(qcom_cpu_spc, idx, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static struct cpuidle_driver qcom_spm_idle_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.name = "qcom_spm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.states[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.enter			= spm_enter_idle_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.exit_latency		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.target_residency	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		.power_usage		= UINT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.name			= "WFI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		.desc			= "ARM WFI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const struct of_device_id qcom_idle_state_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	{ .compatible = "qcom,idle-state-spc", .data = spm_enter_idle_state },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int spm_cpuidle_init(struct cpuidle_driver *drv, int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	memcpy(drv, &qcom_spm_idle_driver, sizeof(*drv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	drv->cpumask = (struct cpumask *)cpumask_of(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* Parse idle states from device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	ret = dt_init_idle_driver(drv, qcom_idle_state_match, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return ret ? : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/* We have atleast one power down mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return qcom_scm_set_warm_boot_addr(cpu_resume_arm, drv->cpumask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct spm_driver_data *spm_get_drv(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		int *spm_cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	struct spm_driver_data *drv = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	struct device_node *cpu_node, *saw_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	bool found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		cpu_node = of_cpu_device_node_get(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		if (!cpu_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		found = (saw_node == pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		of_node_put(saw_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		of_node_put(cpu_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		if (found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		if (drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			*spm_cpu = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct of_device_id spm_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	{ .compatible = "qcom,msm8974-saw2-v2.1-cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	  .data = &spm_reg_8974_8084_cpu },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	{ .compatible = "qcom,apq8084-saw2-v2.1-cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	  .data = &spm_reg_8974_8084_cpu },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	{ .compatible = "qcom,apq8064-saw2-v1.1-cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	  .data = &spm_reg_8064_cpu },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int spm_dev_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct spm_driver_data *drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	const struct of_device_id *match_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	int cpu, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (!qcom_scm_is_available())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	drv = spm_get_drv(pdev, &cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (!drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	platform_set_drvdata(pdev, drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	drv->reg_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (IS_ERR(drv->reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return PTR_ERR(drv->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	match_id = of_match_node(spm_match_table, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (!match_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	drv->reg_data = match_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	ret = spm_cpuidle_init(&drv->cpuidle_driver, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/* Write the SPM sequences first.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	__iowrite32_copy(addr, drv->reg_data->seq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			ARRAY_SIZE(drv->reg_data->seq) / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	 * ..and then the control registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	 * On some SoC if the control registers are written first and if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	 * CPU was held in reset, the reset signal could trigger the SPM state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	 * machine, before the sequences are completely written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	spm_register_write(drv, SPM_REG_PMIC_DATA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 				drv->reg_data->pmic_data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	spm_register_write(drv, SPM_REG_PMIC_DATA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 				drv->reg_data->pmic_data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	/* Set up Standby as the default low power mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	return cpuidle_register(&drv->cpuidle_driver, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int spm_dev_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	struct spm_driver_data *drv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	cpuidle_unregister(&drv->cpuidle_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct platform_driver spm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.probe = spm_dev_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.remove = spm_dev_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.name = "saw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		.of_match_table = spm_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) builtin_platform_driver(spm_driver);