Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * CPU idle Marvell Kirkwood SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * License version 2.  This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * The cpu idle uses wait-for-interrupt and DDR self refresh in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * to implement two idle states -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * #1 wait-for-interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * #2 wait-for-interrupt and DDR self refresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * Maintainer: Jason Cooper <jason@lakedaemon.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * Maintainer: Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/cpuidle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/cpuidle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define KIRKWOOD_MAX_STATES	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void __iomem *ddr_operation_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Actual code that puts the SoC in different idle states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int kirkwood_enter_idle(struct cpuidle_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			       struct cpuidle_driver *drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			       int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	writel(0x7, ddr_operation_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	cpu_do_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static struct cpuidle_driver kirkwood_idle_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	.name			= "kirkwood_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	.owner			= THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	.states[0]		= ARM_CPUIDLE_WFI_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	.states[1]		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		.enter			= kirkwood_enter_idle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		.exit_latency		= 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		.target_residency	= 100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		.name			= "DDR SR",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		.desc			= "WFI and DDR Self Refresh",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	.state_count = KIRKWOOD_MAX_STATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Initialize CPU idle by registering the idle states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int kirkwood_cpuidle_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	ddr_operation_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	if (IS_ERR(ddr_operation_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		return PTR_ERR(ddr_operation_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	return cpuidle_register(&kirkwood_idle_driver, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int kirkwood_cpuidle_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	cpuidle_unregister(&kirkwood_idle_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct platform_driver kirkwood_cpuidle_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	.probe = kirkwood_cpuidle_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	.remove = kirkwood_cpuidle_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 		   .name = "kirkwood_cpuidle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 		   },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) module_platform_driver(kirkwood_cpuidle_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODULE_AUTHOR("Andrew Lunn <andrew@lunn.ch>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MODULE_DESCRIPTION("Kirkwood cpu idle driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MODULE_ALIAS("platform:kirkwood-cpuidle");