^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TI CPUFreq/OPP hw-supported driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016-2017 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Dave Gerlach <d-gerlach@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_opp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define REVISION_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define REVISION_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AM33XX_800M_ARM_MPU_MAX_FREQ 0x1E2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AM43XX_600M_ARM_MPU_MAX_FREQ 0xFFA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRA7_EFUSE_HAS_OD_MPU_OPP 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRA7_EFUSE_HAS_HIGH_MPU_OPP 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRA76_EFUSE_HAS_PLUS_MPU_OPP 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRA7_EFUSE_HAS_ALL_MPU_OPP 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRA76_EFUSE_HAS_ALL_MPU_OPP 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRA7_EFUSE_NOM_MPU_OPP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRA7_EFUSE_OD_MPU_OPP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRA7_EFUSE_HIGH_MPU_OPP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRA76_EFUSE_PLUS_MPU_OPP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OMAP3_CONTROL_DEVICE_STATUS 0x4800244C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OMAP3_CONTROL_IDCODE 0x4830A204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OMAP34xx_ProdID_SKUID 0x4830A20C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VERSION_COUNT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct ti_cpufreq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct ti_cpufreq_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) const char * const *reg_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long (*efuse_xlate)(struct ti_cpufreq_data *opp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long efuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long efuse_fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long efuse_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long efuse_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned long efuse_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long rev_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) bool multi_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct ti_cpufreq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct device *cpu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct device_node *opp_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct regmap *syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) const struct ti_cpufreq_soc_data *soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct opp_table *opp_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static unsigned long amx3_efuse_xlate(struct ti_cpufreq_data *opp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (!efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) efuse = opp_data->soc_data->efuse_fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* AM335x and AM437x use "OPP disable" bits, so invert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return ~efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static unsigned long dra7_efuse_xlate(struct ti_cpufreq_data *opp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long calculated_efuse = DRA7_EFUSE_NOM_MPU_OPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * The efuse on dra7 and am57 parts contains a specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * value indicating the highest available OPP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) switch (efuse) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) case DRA76_EFUSE_HAS_PLUS_MPU_OPP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case DRA76_EFUSE_HAS_ALL_MPU_OPP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) calculated_efuse |= DRA76_EFUSE_PLUS_MPU_OPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case DRA7_EFUSE_HAS_ALL_MPU_OPP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case DRA7_EFUSE_HAS_HIGH_MPU_OPP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) calculated_efuse |= DRA7_EFUSE_HIGH_MPU_OPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case DRA7_EFUSE_HAS_OD_MPU_OPP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) calculated_efuse |= DRA7_EFUSE_OD_MPU_OPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return calculated_efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static unsigned long omap3_efuse_xlate(struct ti_cpufreq_data *opp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned long efuse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* OPP enable bit ("Speed Binned") */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return BIT(efuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct ti_cpufreq_soc_data am3x_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .efuse_xlate = amx3_efuse_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .efuse_fallback = AM33XX_800M_ARM_MPU_MAX_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .efuse_offset = 0x07fc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .efuse_mask = 0x1fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .rev_offset = 0x600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .multi_regulator = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct ti_cpufreq_soc_data am4x_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .efuse_xlate = amx3_efuse_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .efuse_fallback = AM43XX_600M_ARM_MPU_MAX_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .efuse_offset = 0x0610,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .efuse_mask = 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .rev_offset = 0x600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .multi_regulator = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static struct ti_cpufreq_soc_data dra7_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .efuse_xlate = dra7_efuse_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .efuse_offset = 0x020c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .efuse_mask = 0xf80000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .efuse_shift = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .rev_offset = 0x204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .multi_regulator = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * OMAP35x TRM (SPRUF98K):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Control OMAP Status Register 15:0 (Address 0x4800 244C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * to separate between omap3503, omap3515, omap3525, omap3530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * and feature presence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * There are encodings for versions limited to 400/266MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * but we ignore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Not clear if this also holds for omap34xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * some eFuse values e.g. CONTROL_FUSE_OPP1_VDD1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * are stored in the SYSCON register range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Register 0x4830A20C [ProdID.SKUID] [0:3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * 0x0 for normal 600/430MHz device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * 0x8 for 720/520MHz device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Not clear what omap34xx value is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct ti_cpufreq_soc_data omap34xx_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .efuse_xlate = omap3_efuse_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .efuse_offset = OMAP34xx_ProdID_SKUID - OMAP3_SYSCON_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .efuse_shift = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .efuse_mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .multi_regulator = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * AM/DM37x TRM (SPRUGN4M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * CONTROL_IDCODE (0x4830 A204) describes Silicon revisions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Control Device Status Register 15:0 (Address 0x4800 244C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * to separate between am3703, am3715, dm3725, dm3730
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * and feature presence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Speed Binned = Bit 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * 0 800/600 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * 1 1000/800 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * some eFuse values e.g. CONTROL_FUSE_OPP 1G_VDD1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * are stored in the SYSCON register range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * There is no 0x4830A20C [ProdID.SKUID] register (exists but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * seems to always read as 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const char * const omap3_reg_names[] = {"cpu0", "vbb"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static struct ti_cpufreq_soc_data omap36xx_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .reg_names = omap3_reg_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .efuse_xlate = omap3_efuse_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .efuse_shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .efuse_mask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .multi_regulator = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * AM3517 is quite similar to AM/DM37x except that it has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * high speed grade eFuse and no abb ldo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct ti_cpufreq_soc_data am3517_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .efuse_xlate = omap3_efuse_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .efuse_offset = OMAP3_CONTROL_DEVICE_STATUS - OMAP3_SYSCON_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .efuse_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .efuse_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .rev_offset = OMAP3_CONTROL_IDCODE - OMAP3_SYSCON_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .multi_regulator = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * ti_cpufreq_get_efuse() - Parse and return efuse value present on SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @opp_data: pointer to ti_cpufreq_data context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @efuse_value: Set to the value parsed from efuse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Returns error code if efuse not read properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 *efuse_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct device *dev = opp_data->cpu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 efuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) &efuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (ret == -EIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* not a syscon register! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) opp_data->soc_data->efuse_offset, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) efuse = readl(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) iounmap(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) else if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "Failed to read the efuse value from syscon: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) efuse = (efuse & opp_data->soc_data->efuse_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) efuse >>= opp_data->soc_data->efuse_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *efuse_value = opp_data->soc_data->efuse_xlate(opp_data, efuse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * ti_cpufreq_get_rev() - Parse and return rev value present on SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @opp_data: pointer to ti_cpufreq_data context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * @revision_value: Set to the value parsed from revision register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Returns error code if revision not read properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 *revision_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct device *dev = opp_data->cpu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) &revision);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ret == -EIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* not a syscon register! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) void __iomem *regs = ioremap(OMAP3_SYSCON_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) opp_data->soc_data->rev_offset, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) revision = readl(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) iounmap(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) else if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "Failed to read the revision number from syscon: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *revision_value = BIT((revision >> REVISION_SHIFT) & REVISION_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int ti_cpufreq_setup_syscon_register(struct ti_cpufreq_data *opp_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct device *dev = opp_data->cpu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct device_node *np = opp_data->opp_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) opp_data->syscon = syscon_regmap_lookup_by_phandle(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "syscon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (IS_ERR(opp_data->syscon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "\"syscon\" is missing, cannot use OPPv2 table.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return PTR_ERR(opp_data->syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct of_device_id ti_cpufreq_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { .compatible = "ti,am33xx", .data = &am3x_soc_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { .compatible = "ti,am3517", .data = &am3517_soc_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { .compatible = "ti,am43", .data = &am4x_soc_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { .compatible = "ti,dra7", .data = &dra7_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { .compatible = "ti,omap34xx", .data = &omap34xx_soc_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { .compatible = "ti,omap36xx", .data = &omap36xx_soc_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* legacy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { .compatible = "ti,omap3430", .data = &omap34xx_soc_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { .compatible = "ti,omap3630", .data = &omap36xx_soc_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const struct of_device_id *ti_cpufreq_match_node(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) np = of_find_node_by_path("/");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) match = of_match_node(ti_cpufreq_of_match, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int ti_cpufreq_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u32 version[VERSION_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct opp_table *ti_opp_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct ti_cpufreq_data *opp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) const char * const default_reg_names[] = {"vdd", "vbb"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) match = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) opp_data = devm_kzalloc(&pdev->dev, sizeof(*opp_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!opp_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) opp_data->soc_data = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) opp_data->cpu_dev = get_cpu_device(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!opp_data->cpu_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pr_err("%s: Failed to get device for CPU0\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) opp_data->opp_node = dev_pm_opp_of_get_opp_desc_node(opp_data->cpu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (!opp_data->opp_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_info(opp_data->cpu_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "OPP-v2 not supported, cpufreq-dt will attempt to use legacy tables.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) goto register_cpufreq_dt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ret = ti_cpufreq_setup_syscon_register(opp_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) goto fail_put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * OPPs determine whether or not they are supported based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * two metrics:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * 0 - SoC Revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * 1 - eFuse value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret = ti_cpufreq_get_rev(opp_data, &version[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) goto fail_put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = ti_cpufreq_get_efuse(opp_data, &version[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) goto fail_put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ti_opp_table = dev_pm_opp_set_supported_hw(opp_data->cpu_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) version, VERSION_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (IS_ERR(ti_opp_table)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_err(opp_data->cpu_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "Failed to set supported hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ret = PTR_ERR(ti_opp_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) goto fail_put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) opp_data->opp_table = ti_opp_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (opp_data->soc_data->multi_regulator) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) const char * const *reg_names = default_reg_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (opp_data->soc_data->reg_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) reg_names = opp_data->soc_data->reg_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ti_opp_table = dev_pm_opp_set_regulators(opp_data->cpu_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) reg_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ARRAY_SIZE(default_reg_names));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (IS_ERR(ti_opp_table)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_pm_opp_put_supported_hw(opp_data->opp_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = PTR_ERR(ti_opp_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) goto fail_put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) of_node_put(opp_data->opp_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) register_cpufreq_dt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) fail_put_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) of_node_put(opp_data->opp_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int ti_cpufreq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Check to ensure we are on a compatible platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) match = ti_cpufreq_match_node();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) platform_device_register_data(NULL, "ti-cpufreq", -1, match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) sizeof(*match));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) module_init(ti_cpufreq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static struct platform_driver ti_cpufreq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .probe = ti_cpufreq_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .name = "ti-cpufreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) builtin_platform_driver(ti_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MODULE_DESCRIPTION("TI CPUFreq/OPP hw-supported driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MODULE_AUTHOR("Dave Gerlach <d-gerlach@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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