^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <soc/tegra/bpmp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <soc/tegra/bpmp-abi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define KHZ 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define REF_CLK_MHZ 408 /* 408 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define US_DELAY 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define US_DELAY_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CPUFREQ_TBL_STEP_HZ (50 * KHZ * KHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MAX_CNT ~0U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* cpufreq transisition latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA_CPUFREQ_TRANSITION_LATENCY (300 * 1000) /* unit in nanoseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum cluster {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) CLUSTER0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) CLUSTER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) CLUSTER2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) CLUSTER3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MAX_CLUSTERS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct tegra194_cpufreq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) size_t num_clusters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct cpufreq_frequency_table **tables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct tegra_cpu_ctr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 coreclk_cnt, last_coreclk_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 refclk_cnt, last_refclk_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct read_counters_work {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct tegra_cpu_ctr c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct workqueue_struct *read_counters_wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void get_cpu_cluster(void *cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u64 mpidr = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *((uint32_t *)cluster) = MPIDR_AFFINITY_LEVEL(mpidr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Read per-core Read-only system register NVFREQ_FEEDBACK_EL1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * The register provides frequency feedback information to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * determine the average actual frequency a core has run at over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * a period of time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * [31:0] PLLP counter: Counts at fixed frequency (408 MHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * [63:32] Core clock counter: counts on every core clock cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * where the core is architecturally clocking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static u64 read_freq_feedback(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u64 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) asm volatile("mrs %0, s3_0_c15_c0_5" : "=r" (val) : );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static inline u32 map_ndiv_to_freq(struct mrq_cpu_ndiv_limits_response
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *nltbl, u16 ndiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return nltbl->ref_clk_hz / KHZ * ndiv / (nltbl->pdiv * nltbl->mdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void tegra_read_counters(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct read_counters_work *read_counters_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct tegra_cpu_ctr *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * ref_clk_counter(32 bit counter) runs on constant clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * pll_p(408MHz).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * It will take = 2 ^ 32 / 408 MHz to overflow ref clk counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * = 10526880 usec = 10.527 sec to overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Like wise core_clk_counter(32 bit counter) runs on core clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * It's synchronized to crab_clk (cpu_crab_clk) which runs at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * freq of cluster. Assuming max cluster clock ~2000MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * It will take = 2 ^ 32 / 2000 MHz to overflow core clk counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * = ~2.147 sec to overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) read_counters_work = container_of(work, struct read_counters_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) c = &read_counters_work->c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) val = read_freq_feedback();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) c->last_refclk_cnt = lower_32_bits(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) c->last_coreclk_cnt = upper_32_bits(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) udelay(c->delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val = read_freq_feedback();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) c->refclk_cnt = lower_32_bits(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) c->coreclk_cnt = upper_32_bits(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Return instantaneous cpu speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Instantaneous freq is calculated as -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * -Takes sample on every query of getting the freq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * - Read core and ref clock counters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * - Delay for X us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * - Read above cycle counters again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * - Calculates freq by subtracting current and previous counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * divided by the delay time or eqv. of ref_clk_counter in delta time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * - Return Kcycles/second, freq in KHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * delta time period = x sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * = delta ref_clk_counter / (408 * 10^6) sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * freq in Hz = cycles/sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * = (delta cycles / x sec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * = (delta cycles * 408 * 10^6) / delta ref_clk_counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * in KHz = (delta cycles * 408 * 10^3) / delta ref_clk_counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @cpu - logical cpu whose freq to be updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Returns freq in KHz on success, 0 if cpu is offline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static unsigned int tegra194_get_speed_common(u32 cpu, u32 delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct read_counters_work read_counters_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct tegra_cpu_ctr c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 delta_refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 delta_ccnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 rate_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * udelay() is required to reconstruct cpu frequency over an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * observation window. Using workqueue to call udelay() with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * interrupts enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) read_counters_work.c.cpu = cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) read_counters_work.c.delay = delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) INIT_WORK_ONSTACK(&read_counters_work.work, tegra_read_counters);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) queue_work_on(cpu, read_counters_wq, &read_counters_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) flush_work(&read_counters_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) c = read_counters_work.c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (c.coreclk_cnt < c.last_coreclk_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) delta_ccnt = c.coreclk_cnt + (MAX_CNT - c.last_coreclk_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) delta_ccnt = c.coreclk_cnt - c.last_coreclk_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (!delta_ccnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* ref clock is 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (c.refclk_cnt < c.last_refclk_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) delta_refcnt = c.refclk_cnt + (MAX_CNT - c.last_refclk_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) delta_refcnt = c.refclk_cnt - c.last_refclk_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!delta_refcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pr_debug("cpufreq: %d is idle, delta_refcnt: 0\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) rate_mhz = ((unsigned long)(delta_ccnt * REF_CLK_MHZ)) / delta_refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return (rate_mhz * KHZ); /* in KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static unsigned int tegra194_get_speed(u32 cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return tegra194_get_speed_common(cpu, US_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int tegra194_cpufreq_init(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct tegra194_cpufreq_data *data = cpufreq_get_driver_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 cl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) smp_call_function_single(policy->cpu, get_cpu_cluster, &cl, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (cl >= data->num_clusters)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* boot freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) policy->cur = tegra194_get_speed_common(policy->cpu, US_DELAY_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* set same policy for all cpus in a cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) for (cpu = (cl * 2); cpu < ((cl + 1) * 2); cpu++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) cpumask_set_cpu(cpu, policy->cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) policy->freq_table = data->tables[cl];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) policy->cpuinfo.transition_latency = TEGRA_CPUFREQ_TRANSITION_LATENCY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void set_cpu_ndiv(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct cpufreq_frequency_table *tbl = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u64 ndiv_val = (u64)tbl->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) asm volatile("msr s3_0_c15_c0_4, %0" : : "r" (ndiv_val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int tegra194_cpufreq_set_target(struct cpufreq_policy *policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct cpufreq_frequency_table *tbl = policy->freq_table + index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Each core writes frequency in per core register. Then both cores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * in a cluster run at same frequency which is the maximum frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * request out of the values requested by both cores in that cluster.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) on_each_cpu_mask(policy->cpus, set_cpu_ndiv, tbl, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct cpufreq_driver tegra194_cpufreq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .name = "tegra194",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .flags = CPUFREQ_STICKY | CPUFREQ_CONST_LOOPS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) CPUFREQ_NEED_INITIAL_FREQ_CHECK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .verify = cpufreq_generic_frequency_table_verify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .target_index = tegra194_cpufreq_set_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .get = tegra194_get_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .init = tegra194_cpufreq_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .attr = cpufreq_generic_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void tegra194_cpufreq_free_resources(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) destroy_workqueue(read_counters_wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct cpufreq_frequency_table *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) init_freq_table(struct platform_device *pdev, struct tegra_bpmp *bpmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned int cluster_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct cpufreq_frequency_table *freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct mrq_cpu_ndiv_limits_response resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int num_freqs, ndiv, delta_ndiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct mrq_cpu_ndiv_limits_request req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct tegra_bpmp_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u16 freq_table_step_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int err, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) memset(&req, 0, sizeof(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) req.cluster_id = cluster_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) memset(&msg, 0, sizeof(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) msg.mrq = MRQ_CPU_NDIV_LIMITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) msg.tx.data = &req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) msg.tx.size = sizeof(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) msg.rx.data = &resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) msg.rx.size = sizeof(resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) err = tegra_bpmp_transfer(bpmp, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Make sure frequency table step is a multiple of mdiv to match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * vhint table granularity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) freq_table_step_size = resp.mdiv *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DIV_ROUND_UP(CPUFREQ_TBL_STEP_HZ, resp.ref_clk_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dev_dbg(&pdev->dev, "cluster %d: frequency table step size: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) cluster_id, freq_table_step_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) delta_ndiv = resp.ndiv_max - resp.ndiv_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (unlikely(delta_ndiv == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) num_freqs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* We store both ndiv_min and ndiv_max hence the +1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) num_freqs = delta_ndiv / freq_table_step_size + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) num_freqs += (delta_ndiv % freq_table_step_size) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) freq_table = devm_kcalloc(&pdev->dev, num_freqs + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) sizeof(*freq_table), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (!freq_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) for (index = 0, ndiv = resp.ndiv_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ndiv < resp.ndiv_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) index++, ndiv += freq_table_step_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) freq_table[index].driver_data = ndiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) freq_table[index].frequency = map_ndiv_to_freq(&resp, ndiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) freq_table[index].driver_data = resp.ndiv_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) freq_table[index++].frequency = map_ndiv_to_freq(&resp, resp.ndiv_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) freq_table[index].frequency = CPUFREQ_TABLE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int tegra194_cpufreq_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct tegra194_cpufreq_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct tegra_bpmp *bpmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) data->num_clusters = MAX_CLUSTERS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) data->tables = devm_kcalloc(&pdev->dev, data->num_clusters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) sizeof(*data->tables), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!data->tables)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) platform_set_drvdata(pdev, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) bpmp = tegra_bpmp_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (IS_ERR(bpmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return PTR_ERR(bpmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) read_counters_wq = alloc_workqueue("read_counters_wq", __WQ_LEGACY, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (!read_counters_wq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev_err(&pdev->dev, "fail to create_workqueue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) goto put_bpmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) for (i = 0; i < data->num_clusters; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) data->tables[i] = init_freq_table(pdev, bpmp, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (IS_ERR(data->tables[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) err = PTR_ERR(data->tables[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) goto err_free_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) tegra194_cpufreq_driver.driver_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) err = cpufreq_register_driver(&tegra194_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) goto put_bpmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) err_free_res:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) tegra194_cpufreq_free_resources();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) put_bpmp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) tegra_bpmp_put(bpmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int tegra194_cpufreq_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) cpufreq_unregister_driver(&tegra194_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) tegra194_cpufreq_free_resources();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const struct of_device_id tegra194_cpufreq_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { .compatible = "nvidia,tegra194-ccplex", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MODULE_DEVICE_TABLE(of, tegra194_cpufreq_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static struct platform_driver tegra194_ccplex_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .name = "tegra194-cpufreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .of_match_table = tegra194_cpufreq_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .probe = tegra194_cpufreq_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .remove = tegra194_cpufreq_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) module_platform_driver(tegra194_ccplex_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MODULE_AUTHOR("Sumit Gupta <sumitg@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MODULE_DESCRIPTION("NVIDIA Tegra194 cpufreq driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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