Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <soc/tegra/bpmp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <soc/tegra/bpmp-abi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define EDVD_CORE_VOLT_FREQ(core)		(0x20 + (core) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define EDVD_CORE_VOLT_FREQ_F_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define EDVD_CORE_VOLT_FREQ_F_MASK		0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define EDVD_CORE_VOLT_FREQ_V_SHIFT		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) struct tegra186_cpufreq_cluster_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	int cpus[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	unsigned int bpmp_cluster_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define NO_CPU -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static const struct tegra186_cpufreq_cluster_info tegra186_clusters[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	/* Denver cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		.offset = SZ_64K * 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		.cpus = { 1, 2, NO_CPU, NO_CPU },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		.bpmp_cluster_id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	/* A57 cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		.offset = SZ_64K * 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		.cpus = { 0, 3, 4, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		.bpmp_cluster_id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) struct tegra186_cpufreq_cluster {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	const struct tegra186_cpufreq_cluster_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct cpufreq_frequency_table *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u32 ref_clk_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct tegra186_cpufreq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	size_t num_clusters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct tegra186_cpufreq_cluster *clusters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static int tegra186_cpufreq_init(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	for (i = 0; i < data->num_clusters; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		const struct tegra186_cpufreq_cluster_info *info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			cluster->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		int core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		for (core = 0; core < ARRAY_SIZE(info->cpus); core++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			if (info->cpus[core] == policy->cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		if (core == ARRAY_SIZE(info->cpus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		policy->driver_data =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			data->regs + info->offset + EDVD_CORE_VOLT_FREQ(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		policy->freq_table = cluster->table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	policy->cpuinfo.transition_latency = 300 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 				       unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct cpufreq_frequency_table *tbl = policy->freq_table + index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	void __iomem *edvd_reg = policy->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u32 edvd_val = tbl->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	writel(edvd_val, edvd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) static unsigned int tegra186_cpufreq_get(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct tegra186_cpufreq_data *data = cpufreq_get_driver_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct cpufreq_policy *policy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	void __iomem *edvd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	unsigned int i, freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	u32 ndiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	policy = cpufreq_cpu_get(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (!policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	edvd_reg = policy->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	ndiv = readl(edvd_reg) & EDVD_CORE_VOLT_FREQ_F_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	for (i = 0; i < data->num_clusters; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		int core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		for (core = 0; core < ARRAY_SIZE(cluster->info->cpus); core++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			if (cluster->info->cpus[core] != policy->cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			freq = (cluster->ref_clk_khz * ndiv) / cluster->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	cpufreq_cpu_put(policy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	return freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static struct cpufreq_driver tegra186_cpufreq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.name = "tegra186",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.flags = CPUFREQ_STICKY | CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			CPUFREQ_NEED_INITIAL_FREQ_CHECK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.get = tegra186_cpufreq_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.verify = cpufreq_generic_frequency_table_verify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.target_index = tegra186_cpufreq_set_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.init = tegra186_cpufreq_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.attr = cpufreq_generic_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct cpufreq_frequency_table *init_vhint_table(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct platform_device *pdev, struct tegra_bpmp *bpmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct tegra186_cpufreq_cluster *cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct cpufreq_frequency_table *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct mrq_cpu_vhint_request req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct tegra_bpmp_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct cpu_vhint_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	int err, i, j, num_rates = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	dma_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	void *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	virt = dma_alloc_coherent(bpmp->dev, sizeof(*data), &phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 				  GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	if (!virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	data = (struct cpu_vhint_data *)virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	memset(&req, 0, sizeof(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	req.addr = phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	req.cluster_id = cluster->info->bpmp_cluster_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	memset(&msg, 0, sizeof(msg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	msg.mrq = MRQ_CPU_VHINT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	msg.tx.data = &req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	msg.tx.size = sizeof(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	err = tegra_bpmp_transfer(bpmp, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		table = ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	for (i = data->vfloor; i <= data->vceil; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		u16 ndiv = data->ndiv[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		if (ndiv < data->ndiv_min || ndiv > data->ndiv_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		/* Only store lowest voltage index for each rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		if (i > 0 && ndiv == data->ndiv[i - 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		num_rates++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	table = devm_kcalloc(&pdev->dev, num_rates + 1, sizeof(*table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			     GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (!table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		table = ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	cluster->ref_clk_khz = data->ref_clk_hz / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	cluster->div = data->pdiv * data->mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	for (i = data->vfloor, j = 0; i <= data->vceil; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		struct cpufreq_frequency_table *point;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		u16 ndiv = data->ndiv[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		u32 edvd_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		if (ndiv < data->ndiv_min || ndiv > data->ndiv_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		/* Only store lowest voltage index for each rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		if (i > 0 && ndiv == data->ndiv[i - 1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		edvd_val |= i << EDVD_CORE_VOLT_FREQ_V_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		edvd_val |= ndiv << EDVD_CORE_VOLT_FREQ_F_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		point = &table[j++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		point->driver_data = edvd_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		point->frequency = (cluster->ref_clk_khz * ndiv) / cluster->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	table[j].frequency = CPUFREQ_TABLE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	dma_free_coherent(bpmp->dev, sizeof(*data), virt, phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int tegra186_cpufreq_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct tegra186_cpufreq_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct tegra_bpmp *bpmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	unsigned int i = 0, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	data->clusters = devm_kcalloc(&pdev->dev, ARRAY_SIZE(tegra186_clusters),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				      sizeof(*data->clusters), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (!data->clusters)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	data->num_clusters = ARRAY_SIZE(tegra186_clusters);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	bpmp = tegra_bpmp_get(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (IS_ERR(bpmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return PTR_ERR(bpmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	data->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (IS_ERR(data->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		err = PTR_ERR(data->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		goto put_bpmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	for (i = 0; i < data->num_clusters; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		struct tegra186_cpufreq_cluster *cluster = &data->clusters[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		cluster->info = &tegra186_clusters[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		cluster->table = init_vhint_table(pdev, bpmp, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		if (IS_ERR(cluster->table)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			err = PTR_ERR(cluster->table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			goto put_bpmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	tegra186_cpufreq_driver.driver_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	err = cpufreq_register_driver(&tegra186_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) put_bpmp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	tegra_bpmp_put(bpmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int tegra186_cpufreq_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	cpufreq_unregister_driver(&tegra186_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const struct of_device_id tegra186_cpufreq_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	{ .compatible = "nvidia,tegra186-ccplex-cluster", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MODULE_DEVICE_TABLE(of, tegra186_cpufreq_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static struct platform_driver tegra186_cpufreq_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.name = "tegra186-cpufreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.of_match_table = tegra186_cpufreq_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.probe = tegra186_cpufreq_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.remove = tegra186_cpufreq_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) module_platform_driver(tegra186_cpufreq_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MODULE_DESCRIPTION("NVIDIA Tegra186 cpufreq driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MODULE_LICENSE("GPL v2");