^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Tegra 124 cpufreq driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_opp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct tegra124_cpufreq_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct clk *cpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk *pllp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk *pllx_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct clk *dfll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct platform_device *cpufreq_dt_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static int tegra124_cpu_switch_to_dfll(struct tegra124_cpufreq_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct clk *orig_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ret = clk_set_rate(priv->dfll_clk, clk_get_rate(priv->cpu_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) orig_parent = clk_get_parent(priv->cpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) clk_set_parent(priv->cpu_clk, priv->pllp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ret = clk_prepare_enable(priv->dfll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) clk_set_parent(priv->cpu_clk, priv->dfll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) clk_set_parent(priv->cpu_clk, orig_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int tegra124_cpufreq_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct tegra124_cpufreq_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct device *cpu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct platform_device_info cpufreq_dt_devinfo = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) cpu_dev = get_cpu_device(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (!cpu_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) np = of_cpu_device_node_get(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) priv->cpu_clk = of_clk_get_by_name(np, "cpu_g");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (IS_ERR(priv->cpu_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ret = PTR_ERR(priv->cpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) goto out_put_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) priv->dfll_clk = of_clk_get_by_name(np, "dfll");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (IS_ERR(priv->dfll_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ret = PTR_ERR(priv->dfll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) goto out_put_cpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) priv->pllx_clk = of_clk_get_by_name(np, "pll_x");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (IS_ERR(priv->pllx_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = PTR_ERR(priv->pllx_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) goto out_put_dfll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) priv->pllp_clk = of_clk_get_by_name(np, "pll_p");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (IS_ERR(priv->pllp_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = PTR_ERR(priv->pllp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) goto out_put_pllx_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ret = tegra124_cpu_switch_to_dfll(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) goto out_put_pllp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) cpufreq_dt_devinfo.name = "cpufreq-dt";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) cpufreq_dt_devinfo.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) priv->cpufreq_dt_pdev =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) platform_device_register_full(&cpufreq_dt_devinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (IS_ERR(priv->cpufreq_dt_pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ret = PTR_ERR(priv->cpufreq_dt_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) goto out_put_pllp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) out_put_pllp_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clk_put(priv->pllp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) out_put_pllx_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) clk_put(priv->pllx_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) out_put_dfll_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) clk_put(priv->dfll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) out_put_cpu_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) clk_put(priv->cpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) out_put_np:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int __maybe_unused tegra124_cpufreq_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * PLLP rate 408Mhz is below the CPU Fmax at Vmin and is safe to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * use during suspend and resume. So, switch the CPU clock source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * to PLLP and disable DFLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) err = clk_set_parent(priv->cpu_clk, priv->pllp_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_err(dev, "failed to reparent to PLLP: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) clk_disable_unprepare(priv->dfll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int __maybe_unused tegra124_cpufreq_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Warmboot code powers up the CPU with PLLP clock source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * Enable DFLL clock and switch CPU clock source back to DFLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) err = clk_prepare_enable(priv->dfll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dev_err(dev, "failed to enable DFLL clock for CPU: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) goto disable_cpufreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) err = clk_set_parent(priv->cpu_clk, priv->dfll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dev_err(dev, "failed to reparent to DFLL clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) goto disable_dfll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) disable_dfll:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) clk_disable_unprepare(priv->dfll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) disable_cpufreq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) disable_cpufreq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct dev_pm_ops tegra124_cpufreq_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) tegra124_cpufreq_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct platform_driver tegra124_cpufreq_platdrv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .driver.name = "cpufreq-tegra124",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .driver.pm = &tegra124_cpufreq_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .probe = tegra124_cpufreq_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int __init tegra_cpufreq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!(of_machine_is_compatible("nvidia,tegra124") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) of_machine_is_compatible("nvidia,tegra210")))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Platform driver+device required for handling EPROBE_DEFER with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * the regulator and the DFLL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ret = platform_driver_register(&tegra124_cpufreq_platdrv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pdev = platform_device_register_simple("cpufreq-tegra124", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (IS_ERR(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) platform_driver_unregister(&tegra124_cpufreq_platdrv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return PTR_ERR(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) module_init(tegra_cpufreq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MODULE_AUTHOR("Tuomas Tynkkynen <ttynkkynen@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MODULE_DESCRIPTION("cpufreq driver for NVIDIA Tegra124");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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