Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Match running platform with pre-defined OPP values for CPUFreq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Ajit Pal Singh <ajitpal.singh@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *         Lee Jones <lee.jones@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2015 STMicroelectronics (R&D) Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/pm_opp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define VERSION_ELEMENTS	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MAX_PCODE_NAME_LEN	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define VERSION_SHIFT		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define HW_INFO_INDEX		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MAJOR_ID_INDEX		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MINOR_ID_INDEX		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * Only match on "suitable for ALL versions" entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * This will be used with the BIT() macro.  It sets the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * top bit of a 32bit value and is equal to 0x80000000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DEFAULT_VERSION		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	PCODE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	SUBSTRATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	DVFS_MAX_REGFIELDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * struct sti_cpufreq_ddata - ST CPUFreq Driver Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * @cpu:		CPU's OF node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * @syscfg_eng:		Engineering Syscon register map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  * @syscfg:		Syscon register map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static struct sti_cpufreq_ddata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct device *cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct regmap *syscfg_eng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct regmap *syscfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) } ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static int sti_cpufreq_fetch_major(void) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct device_node *np = ddata.cpu->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct device *dev = ddata.cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	unsigned int major_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	unsigned int socid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	ret = of_property_read_u32_index(np, "st,syscfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 					 MAJOR_ID_INDEX, &major_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		dev_err(dev, "No major number offset provided in %pOF [%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 			np, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	ret = regmap_read(ddata.syscfg, major_offset, &socid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		dev_err(dev, "Failed to read major number from syscon [%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	return ((socid >> VERSION_SHIFT) & 0xf) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static int sti_cpufreq_fetch_minor(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct device *dev = ddata.cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	unsigned int minor_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	unsigned int minid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	ret = of_property_read_u32_index(np, "st,syscfg-eng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 					 MINOR_ID_INDEX, &minor_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			"No minor number offset provided %pOF [%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			np, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	ret = regmap_read(ddata.syscfg_eng, minor_offset, &minid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			"Failed to read the minor number from syscon [%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return minid & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int sti_cpufreq_fetch_regmap_field(const struct reg_field *reg_fields,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 					  int hw_info_offset, int field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct regmap_field *regmap_field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct reg_field reg_field = reg_fields[field];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct device *dev = ddata.cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	reg_field.reg = hw_info_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	regmap_field = devm_regmap_field_alloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 					       ddata.syscfg_eng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 					       reg_field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (IS_ERR(regmap_field)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		dev_err(dev, "Failed to allocate reg field\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		return PTR_ERR(regmap_field);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	ret = regmap_field_read(regmap_field, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		dev_err(dev, "Failed to read %s code\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			field ? "SUBSTRATE" : "PCODE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const struct reg_field sti_stih407_dvfs_regfields[DVFS_MAX_REGFIELDS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	[PCODE]		= REG_FIELD(0, 16, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	[SUBSTRATE]	= REG_FIELD(0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct reg_field *sti_cpufreq_match(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (of_machine_is_compatible("st,stih407") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	    of_machine_is_compatible("st,stih410") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	    of_machine_is_compatible("st,stih418"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		return sti_stih407_dvfs_regfields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int sti_cpufreq_set_opp_info(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct device *dev = ddata.cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	const struct reg_field *reg_fields;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	unsigned int hw_info_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	unsigned int version[VERSION_ELEMENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	int pcode, substrate, major, minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	char name[MAX_PCODE_NAME_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct opp_table *opp_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	reg_fields = sti_cpufreq_match();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (!reg_fields) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		dev_err(dev, "This SoC doesn't support voltage scaling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	ret = of_property_read_u32_index(np, "st,syscfg-eng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 					 HW_INFO_INDEX, &hw_info_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		dev_warn(dev, "Failed to read HW info offset from DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		substrate = DEFAULT_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		pcode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		goto use_defaults;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	pcode = sti_cpufreq_fetch_regmap_field(reg_fields,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 					       hw_info_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 					       PCODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (pcode < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		dev_warn(dev, "Failed to obtain process code\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		/* Use default pcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		pcode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	substrate = sti_cpufreq_fetch_regmap_field(reg_fields,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 						   hw_info_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 						   SUBSTRATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (substrate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		dev_warn(dev, "Failed to obtain substrate code\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		/* Use default substrate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		substrate = DEFAULT_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) use_defaults:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	major = sti_cpufreq_fetch_major();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (major < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		dev_err(dev, "Failed to obtain major version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		/* Use default major number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		major = DEFAULT_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	minor = sti_cpufreq_fetch_minor();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (minor < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		dev_err(dev, "Failed to obtain minor version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		/* Use default minor number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		minor = DEFAULT_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	snprintf(name, MAX_PCODE_NAME_LEN, "pcode%d", pcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	opp_table = dev_pm_opp_set_prop_name(dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (IS_ERR(opp_table)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		dev_err(dev, "Failed to set prop name\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		return PTR_ERR(opp_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	version[0] = BIT(major);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	version[1] = BIT(minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	version[2] = BIT(substrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	opp_table = dev_pm_opp_set_supported_hw(dev, version, VERSION_ELEMENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (IS_ERR(opp_table)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		dev_err(dev, "Failed to set supported hardware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return PTR_ERR(opp_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	dev_dbg(dev, "pcode: %d major: %d minor: %d substrate: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		pcode, major, minor, substrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	dev_dbg(dev, "version[0]: %x version[1]: %x version[2]: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		version[0], version[1], version[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int sti_cpufreq_fetch_syscon_registers(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct device *dev = ddata.cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	ddata.syscfg = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (IS_ERR(ddata.syscfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		dev_err(dev,  "\"st,syscfg\" not supplied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		return PTR_ERR(ddata.syscfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	ddata.syscfg_eng = syscon_regmap_lookup_by_phandle(np, "st,syscfg-eng");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (IS_ERR(ddata.syscfg_eng)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		dev_err(dev, "\"st,syscfg-eng\" not supplied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return PTR_ERR(ddata.syscfg_eng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int sti_cpufreq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if ((!of_machine_is_compatible("st,stih407")) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		(!of_machine_is_compatible("st,stih410")) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		(!of_machine_is_compatible("st,stih418")))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	ddata.cpu = get_cpu_device(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (!ddata.cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		dev_err(ddata.cpu, "Failed to get device for CPU0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		goto skip_voltage_scaling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (!of_get_property(ddata.cpu->of_node, "operating-points-v2", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		dev_err(ddata.cpu, "OPP-v2 not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		goto skip_voltage_scaling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	ret = sti_cpufreq_fetch_syscon_registers();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		goto skip_voltage_scaling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	ret = sti_cpufreq_set_opp_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		goto register_cpufreq_dt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) skip_voltage_scaling:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	dev_err(ddata.cpu, "Not doing voltage scaling\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) register_cpufreq_dt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) module_init(sti_cpufreq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const struct of_device_id __maybe_unused sti_cpufreq_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	{ .compatible = "st,stih407" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	{ .compatible = "st,stih410" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MODULE_DEVICE_TABLE(of, sti_cpufreq_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_DESCRIPTION("STMicroelectronics CPUFreq/OPP driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MODULE_AUTHOR("Ajitpal Singh <ajitpal.singh@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_AUTHOR("Lee Jones <lee.jones@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_LICENSE("GPL v2");