^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Library for common functions for Intel SpeedStep v.1 and v.2 support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/msr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/tsc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "speedstep-lib.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PFX "speedstep-lib: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int relaxed_check;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define relaxed_check 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * GET PROCESSOR CORE SPEED IN KHZ *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static unsigned int pentium3_get_frequency(enum speedstep_processor processor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int ratio; /* Frequency Multiplier (x10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u8 bitmap; /* power on configuration bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [27, 25:22] (in MSR 0x2a) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) } msr_decode_mult[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { 30, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { 35, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { 40, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { 45, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { 50, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { 55, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { 60, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { 65, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { 70, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { 75, 0x0d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { 80, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { 85, 0x26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { 90, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { 100, 0x2b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) { 0, 0xff } /* error or unknown value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int value; /* Front Side Bus speed in MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 bitmap; /* power on configuration bits [18: 19]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) (in MSR 0x2a) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) } msr_decode_fsb[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { 66, 0x0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { 100, 0x2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 133, 0x1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { 0, 0xff}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 msr_lo, msr_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int i = 0, j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* read MSR 0x2a - we only need the low 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pr_debug("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) msr_tmp = msr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* decode the FSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) msr_tmp &= 0x00c0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) msr_tmp >>= 18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) while (msr_tmp != msr_decode_fsb[i].bitmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (msr_decode_fsb[i].bitmap == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* decode the multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (processor == SPEEDSTEP_CPU_PIII_C_EARLY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) pr_debug("workaround for early PIIIs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) msr_lo &= 0x03c00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) msr_lo &= 0x0bc00000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) msr_lo >>= 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) while (msr_lo != msr_decode_mult[j].bitmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (msr_decode_mult[j].bitmap == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pr_debug("speed is %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) (msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return msr_decode_mult[j].ratio * msr_decode_fsb[i].value * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static unsigned int pentiumM_get_frequency(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 msr_lo, msr_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pr_debug("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo, msr_tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* see table B-2 of 24547212.pdf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (msr_lo & 0x00040000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) printk(KERN_DEBUG PFX "PM - invalid FSB: 0x%x 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) msr_lo, msr_tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) msr_tmp = (msr_lo >> 22) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pr_debug("bits 22-26 are 0x%x, speed is %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) msr_tmp, (msr_tmp * 100 * 1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return msr_tmp * 100 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static unsigned int pentium_core_get_frequency(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 fsb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 msr_lo, msr_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) rdmsr(MSR_FSB_FREQ, msr_lo, msr_tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* see table B-2 of 25366920.pdf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) switch (msr_lo & 0x07) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) fsb = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) fsb = 133333;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) fsb = 166667;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) fsb = 200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) fsb = 266667;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) fsb = 333333;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pr_err("PCORE - MSR_FSB_FREQ undefined value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pr_debug("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) msr_lo, msr_tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) msr_tmp = (msr_lo >> 22) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pr_debug("bits 22-26 are 0x%x, speed is %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) msr_tmp, (msr_tmp * fsb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = (msr_tmp * fsb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static unsigned int pentium4_get_frequency(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct cpuinfo_x86 *c = &boot_cpu_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 msr_lo, msr_hi, mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int fsb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u8 fsb_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Pentium 4 Model 0 and 1 do not have the Core Clock Frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * to System Bus Frequency Ratio Field in the Processor Frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Configuration Register of the MSR. Therefore the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * frequency cannot be calculated and has to be measured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (c->x86_model < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return cpu_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) rdmsr(0x2c, msr_lo, msr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pr_debug("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo, msr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* decode the FSB: see IA-32 Intel (C) Architecture Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * Developer's Manual, Volume 3: System Prgramming Guide,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * revision #12 in Table B-1: MSRs in the Pentium 4 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Intel Xeon Processors, on page B-4 and B-5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) fsb_code = (msr_lo >> 16) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) switch (fsb_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) fsb = 100 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) fsb = 13333 * 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) fsb = 200 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (!fsb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) printk(KERN_DEBUG PFX "couldn't detect FSB speed. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "Please send an e-mail to <linux@brodo.de>\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Multiplier. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) mult = msr_lo >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pr_debug("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) fsb, mult, (fsb * mult));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = (fsb * mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Warning: may get called from smp_call_function_single. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int speedstep_get_frequency(enum speedstep_processor processor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) switch (processor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case SPEEDSTEP_CPU_PCORE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return pentium_core_get_frequency();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case SPEEDSTEP_CPU_PM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return pentiumM_get_frequency();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case SPEEDSTEP_CPU_P4D:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case SPEEDSTEP_CPU_P4M:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return pentium4_get_frequency();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) case SPEEDSTEP_CPU_PIII_T:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case SPEEDSTEP_CPU_PIII_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) case SPEEDSTEP_CPU_PIII_C_EARLY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return pentium3_get_frequency(processor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) EXPORT_SYMBOL_GPL(speedstep_get_frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * DETECT SPEEDSTEP-CAPABLE PROCESSOR *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) *********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Keep in sync with the x86_cpu_id tables in the different modules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) enum speedstep_processor speedstep_detect_processor(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct cpuinfo_x86 *c = &cpu_data(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 ebx, msr_lo, msr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pr_debug("x86: %x, model: %x\n", c->x86, c->x86_model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if ((c->x86_vendor != X86_VENDOR_INTEL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ((c->x86 != 6) && (c->x86 != 0xF)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (c->x86 == 0xF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Intel Mobile Pentium 4-M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * or Intel Mobile Pentium 4 with 533 MHz FSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (c->x86_model != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ebx = cpuid_ebx(0x00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ebx &= 0x000000FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pr_debug("ebx value is %x, x86_stepping is %x\n", ebx, c->x86_stepping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) switch (c->x86_stepping) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * B-stepping [M-P4-M]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * sample has ebx = 0x0f, production has 0x0e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if ((ebx == 0x0e) || (ebx == 0x0f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return SPEEDSTEP_CPU_P4M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * C-stepping [M-P4-M]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * needs to have ebx=0x0e, else it's a celeron:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * cf. 25130917.pdf / page 7, footnote 5 even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * though 25072120.pdf / page 7 doesn't say
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * samples are only of B-stepping...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (ebx == 0x0e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return SPEEDSTEP_CPU_P4M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * D-stepping [M-P4-M or M-P4/533]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * this is totally strange: CPUID 0x0F29 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * The latter need to be sorted out as they don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * support speedstep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * Celerons with CPUID 0x0F29 may have either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * specific.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * M-P4-Ms may have either ebx=0xe or 0xf [see above]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * also, M-P4M HTs have ebx=0x8, too
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * For now, they are distinguished by the model_id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if ((ebx == 0x0e) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) (strstr(c->x86_model_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "Mobile Intel(R) Pentium(R) 4") != NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return SPEEDSTEP_CPU_P4M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) switch (c->x86_model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case 0x0B: /* Intel PIII [Tualatin] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* cpuid_ebx(1) is 0x04 for desktop PIII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * 0x06 for mobile PIII-M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ebx = cpuid_ebx(0x00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pr_debug("ebx is %x\n", ebx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ebx &= 0x000000FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ebx != 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* So far all PIII-M processors support SpeedStep. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * Intel's 24540640.pdf of June 2003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return SPEEDSTEP_CPU_PIII_T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case 0x08: /* Intel PIII [Coppermine] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* all mobile PIII Coppermines have FSB 100 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * ==> sort out a few desktop PIIIs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) rdmsr(MSR_IA32_EBL_CR_POWERON, msr_lo, msr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) pr_debug("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) msr_lo, msr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) msr_lo &= 0x00c0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (msr_lo != 0x0080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * If the processor is a mobile version,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * platform ID has bit 50 set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * it has SpeedStep technology if either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * bit 56 or 57 is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) rdmsr(MSR_IA32_PLATFORM_ID, msr_lo, msr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pr_debug("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) msr_lo, msr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if ((msr_hi & (1<<18)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) (relaxed_check ? 1 : (msr_hi & (3<<24)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (c->x86_stepping == 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pr_debug("early PIII version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return SPEEDSTEP_CPU_PIII_C_EARLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return SPEEDSTEP_CPU_PIII_C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) EXPORT_SYMBOL_GPL(speedstep_detect_processor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /*********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * DETECT SPEEDSTEP SPEEDS *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) *********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned int speedstep_get_freqs(enum speedstep_processor processor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned int *low_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned int *high_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned int *transition_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) void (*set_state) (unsigned int state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned int prev_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ktime_t tv1, tv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if ((!processor) || (!low_speed) || (!high_speed) || (!set_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pr_debug("trying to determine both speeds\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* get current speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) prev_speed = speedstep_get_frequency(processor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (!prev_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pr_debug("previous speed is %u\n", prev_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* switch to low state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) set_state(SPEEDSTEP_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) *low_speed = speedstep_get_frequency(processor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!*low_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) pr_debug("low speed is %u\n", *low_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* start latency measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (transition_latency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) tv1 = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* switch to high state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) set_state(SPEEDSTEP_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* end latency measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (transition_latency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) tv2 = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *high_speed = speedstep_get_frequency(processor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (!*high_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pr_debug("high speed is %u\n", *high_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (*low_speed == *high_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* switch to previous state, if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (*high_speed != prev_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) set_state(SPEEDSTEP_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (transition_latency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) *transition_latency = ktime_to_us(ktime_sub(tv2, tv1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pr_debug("transition latency is %u uSec\n", *transition_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* convert uSec to nSec and add 20% for safety reasons */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) *transition_latency *= 1200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* check if the latency measurement is too high or too low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * and set it to a safe value (500uSec) in that case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (*transition_latency > 10000000 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) *transition_latency < 50000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pr_warn("frequency transition measured seems out of range (%u nSec), falling back to a safe one of %u nSec\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) *transition_latency, 500000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) *transition_latency = 500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) EXPORT_SYMBOL_GPL(speedstep_get_freqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) module_param(relaxed_check, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MODULE_PARM_DESC(relaxed_check,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) "Don't do all checks for speedstep capability.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MODULE_AUTHOR("Dominik Brodowski <linux@brodo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MODULE_DESCRIPTION("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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