^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * (C) 2001 Dave Jones, Arjan van de ven.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based upon reverse engineered information, and on Intel documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * for chipsets ICH2-M and ICH3-M.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Many thanks to Ducrot Bruno for finding and fixing the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * "missing link" for ICH2-M/ICH3-M support, and to Thomas Winkler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * for extensive testing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * SPEEDSTEP - DEFINITIONS *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *********************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/cpu_device_id.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "speedstep-lib.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* speedstep_chipset:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * It is necessary to know which chipset is used. As accesses to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * this device occur at various places in this module, we need a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * static struct pci_dev * pointing to that device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct pci_dev *speedstep_chipset_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* speedstep_processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static enum speedstep_processor speedstep_processor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static u32 pmbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * There are only two frequency states for each processor. Values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * are in kHz for the time being.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct cpufreq_frequency_table speedstep_freqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {0, SPEEDSTEP_HIGH, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {0, SPEEDSTEP_LOW, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {0, 0, CPUFREQ_TABLE_END},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * speedstep_find_register - read the PMBASE address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Returns: -ENODEV if no register could be found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int speedstep_find_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (!speedstep_chipset_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* get PMBASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pci_read_config_dword(speedstep_chipset_dev, 0x40, &pmbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (!(pmbase & 0x01)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pr_err("could not find speedstep register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pmbase &= 0xFFFFFFFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!pmbase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pr_err("could not find speedstep register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pr_debug("pmbase is 0x%x\n", pmbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * speedstep_set_state - set the SpeedStep state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @state: new processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Tries to change the SpeedStep state. Can be called from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * smp_call_function_single.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void speedstep_set_state(unsigned int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 pm2_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (state > 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Disable IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* read state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) value = inb(pmbase + 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* write new state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) value &= 0xFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) value |= state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pr_debug("writing 0x%x to pmbase 0x%x + 0x50\n", value, pmbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Disable bus master arbitration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pm2_blk = inb(pmbase + 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) pm2_blk |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) outb(pm2_blk, (pmbase + 0x20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Actual transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) outb(value, (pmbase + 0x50));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Restore bus master arbitration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pm2_blk &= 0xfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) outb(pm2_blk, (pmbase + 0x20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* check if transition was successful */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) value = inb(pmbase + 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Enable IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pr_debug("read at pmbase 0x%x + 0x50 returned 0x%x\n", pmbase, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (state == (value & 0x1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) pr_debug("change to %u MHz succeeded\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) speedstep_get_frequency(speedstep_processor) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pr_err("change failed - I/O error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Wrapper for smp_call_function_single. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void _speedstep_set_state(void *_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) speedstep_set_state(*(unsigned int *)_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * speedstep_activate - activate SpeedStep control in the chipset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * Tries to activate the SpeedStep status and control registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * Returns -EINVAL on an unsupported chipset, and zero on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int speedstep_activate(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u16 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (!speedstep_chipset_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pci_read_config_word(speedstep_chipset_dev, 0x00A0, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (!(value & 0x08)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) value |= 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pr_debug("activating SpeedStep (TM) registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) pci_write_config_word(speedstep_chipset_dev, 0x00A0, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * speedstep_detect_chipset - detect the Southbridge which contains SpeedStep logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Detects ICH2-M, ICH3-M and ICH4-M so far. The pci_dev points to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * the LPC bridge / PM module which contains all power-management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * functions. Returns the SPEEDSTEP_CHIPSET_-number for the detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * chipset, or zero on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static unsigned int speedstep_detect_chipset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PCI_DEVICE_ID_INTEL_82801DB_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (speedstep_chipset_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 4; /* 4-M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PCI_DEVICE_ID_INTEL_82801CA_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (speedstep_chipset_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 3; /* 3-M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) speedstep_chipset_dev = pci_get_subsys(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PCI_DEVICE_ID_INTEL_82801BA_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (speedstep_chipset_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* speedstep.c causes lockups on Dell Inspirons 8000 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * 8100 which use a pretty old revision of the 82815
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * host bridge. Abort on these systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct pci_dev *hostbridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) hostbridge = pci_get_subsys(PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PCI_DEVICE_ID_INTEL_82815_MC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!hostbridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 2; /* 2-M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (hostbridge->revision < 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pr_debug("hostbridge does not support speedstep\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) speedstep_chipset_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pci_dev_put(hostbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pci_dev_put(hostbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return 2; /* 2-M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static void get_freq_data(void *_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned int *speed = _speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *speed = speedstep_get_frequency(speedstep_processor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static unsigned int speedstep_get(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* You're supposed to ensure CPU is online. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) BUG_ON(smp_call_function_single(cpu, get_freq_data, &speed, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pr_debug("detected %u kHz as current frequency\n", speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * speedstep_target - set a new CPUFreq policy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @policy: new policy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @index: index of target frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * Sets a new CPUFreq policy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int speedstep_target(struct cpufreq_policy *policy, unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned int policy_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) smp_call_function_single(policy_cpu, _speedstep_set_state, &index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct get_freqs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct cpufreq_policy *policy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void get_freqs_on_cpu(void *_get_freqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct get_freqs *get_freqs = _get_freqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) get_freqs->ret =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) speedstep_get_freqs(speedstep_processor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) &speedstep_freqs[SPEEDSTEP_LOW].frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) &speedstep_freqs[SPEEDSTEP_HIGH].frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) &get_freqs->policy->cpuinfo.transition_latency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) &speedstep_set_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int speedstep_cpu_init(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int policy_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct get_freqs gf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* only run on CPU to be set, or on its sibling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) cpumask_copy(policy->cpus, topology_sibling_cpumask(policy->cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* detect low and high frequency and transition latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) gf.policy = policy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) smp_call_function_single(policy_cpu, get_freqs_on_cpu, &gf, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (gf.ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return gf.ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) policy->freq_table = speedstep_freqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static struct cpufreq_driver speedstep_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .name = "speedstep-ich",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .verify = cpufreq_generic_frequency_table_verify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .target_index = speedstep_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .init = speedstep_cpu_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .get = speedstep_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .attr = cpufreq_generic_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct x86_cpu_id ss_smi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) X86_MATCH_VENDOR_FAM_MODEL(INTEL, 6, 0x8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) X86_MATCH_VENDOR_FAM_MODEL(INTEL, 6, 0xb, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) X86_MATCH_VENDOR_FAM_MODEL(INTEL, 15, 0x2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * speedstep_init - initializes the SpeedStep CPUFreq driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * Initializes the SpeedStep support. Returns -ENODEV on unsupported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * devices, -EINVAL on problems during initiatization, and zero on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int __init speedstep_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!x86_match_cpu(ss_smi_ids))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* detect processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) speedstep_processor = speedstep_detect_processor();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (!speedstep_processor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pr_debug("Intel(R) SpeedStep(TM) capable processor "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* detect chipset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (!speedstep_detect_chipset()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pr_debug("Intel(R) SpeedStep(TM) for this chipset not "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "(yet) available.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* activate speedstep support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (speedstep_activate()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pci_dev_put(speedstep_chipset_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (speedstep_find_register())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return cpufreq_register_driver(&speedstep_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * speedstep_exit - unregisters SpeedStep support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * Unregisters SpeedStep support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static void __exit speedstep_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pci_dev_put(speedstep_chipset_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) cpufreq_unregister_driver(&speedstep_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MODULE_AUTHOR("Dave Jones, Dominik Brodowski <linux@brodo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MODULE_DESCRIPTION("Speedstep driver for Intel mobile processors on chipsets "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "with ICH-M southbridges.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) module_init(speedstep_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) module_exit(speedstep_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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