^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * M (part of the Centrino chipset).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Since the original Pentium M, most new Intel CPUs support Enhanced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * SpeedStep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Despite the "SpeedStep" in the name, this is almost entirely unlike
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * traditional SpeedStep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Modelled on speedstep.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sched.h> /* current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/msr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/cpufeature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/cpu_device_id.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MAINTAINER "linux-pm@vger.kernel.org"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define INTEL_MSR_RANGE (0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct cpu_id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) __u8 x86; /* CPU family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) __u8 x86_model; /* model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) __u8 x86_stepping; /* stepping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) CPU_BANIAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) CPU_DOTHAN_A1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) CPU_DOTHAN_A2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) CPU_DOTHAN_B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) CPU_MP4HT_D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) CPU_MP4HT_E0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const struct cpu_id cpu_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) [CPU_BANIAS] = { 6, 9, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) [CPU_DOTHAN_A1] = { 6, 13, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) [CPU_DOTHAN_A2] = { 6, 13, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) [CPU_DOTHAN_B0] = { 6, 13, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) [CPU_MP4HT_D0] = {15, 3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) [CPU_MP4HT_E0] = {15, 4, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define N_IDS ARRAY_SIZE(cpu_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct cpu_model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) const struct cpu_id *cpu_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) const char *model_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned max_freq; /* max clock in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const struct cpu_id *x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Operating points for current CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static DEFINE_PER_CPU(struct cpu_model *, centrino_model);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static DEFINE_PER_CPU(const struct cpu_id *, centrino_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct cpufreq_driver centrino_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Computes the correct form for IA32_PERF_CTL MSR for a particular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) frequency/voltage operating point; frequency in MHz, volts in mV.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) This is stored as "driver_data" in the structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OP(mhz, mv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .frequency = (mhz) * 1000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * These voltage tables were derived from the Intel Pentium M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * datasheet, document 25261202.pdf, Table 5. I have verified they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * M.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static struct cpufreq_frequency_table banias_900[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) OP(600, 844),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) OP(800, 988),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) OP(900, 1004),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { .frequency = CPUFREQ_TABLE_END }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct cpufreq_frequency_table banias_1000[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) OP(600, 844),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) OP(800, 972),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) OP(900, 988),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) OP(1000, 1004),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { .frequency = CPUFREQ_TABLE_END }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct cpufreq_frequency_table banias_1100[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) OP( 600, 956),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) OP( 800, 1020),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) OP( 900, 1100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) OP(1000, 1164),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) OP(1100, 1180),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { .frequency = CPUFREQ_TABLE_END }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct cpufreq_frequency_table banias_1200[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) OP( 600, 956),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) OP( 800, 1004),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) OP( 900, 1020),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) OP(1000, 1100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) OP(1100, 1164),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) OP(1200, 1180),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { .frequency = CPUFREQ_TABLE_END }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Intel Pentium M processor 1.30GHz (Banias) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct cpufreq_frequency_table banias_1300[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) OP( 600, 956),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) OP( 800, 1260),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) OP(1000, 1292),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) OP(1200, 1356),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) OP(1300, 1388),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { .frequency = CPUFREQ_TABLE_END }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Intel Pentium M processor 1.40GHz (Banias) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct cpufreq_frequency_table banias_1400[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) OP( 600, 956),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) OP( 800, 1180),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) OP(1000, 1308),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) OP(1200, 1436),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) OP(1400, 1484),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { .frequency = CPUFREQ_TABLE_END }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Intel Pentium M processor 1.50GHz (Banias) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct cpufreq_frequency_table banias_1500[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) OP( 600, 956),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) OP( 800, 1116),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) OP(1000, 1228),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) OP(1200, 1356),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) OP(1400, 1452),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) OP(1500, 1484),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { .frequency = CPUFREQ_TABLE_END }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Intel Pentium M processor 1.60GHz (Banias) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct cpufreq_frequency_table banias_1600[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) OP( 600, 956),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) OP( 800, 1036),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) OP(1000, 1164),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) OP(1200, 1276),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) OP(1400, 1420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) OP(1600, 1484),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { .frequency = CPUFREQ_TABLE_END }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Intel Pentium M processor 1.70GHz (Banias) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static struct cpufreq_frequency_table banias_1700[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) OP( 600, 956),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) OP( 800, 1004),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) OP(1000, 1116),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) OP(1200, 1228),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) OP(1400, 1308),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) OP(1700, 1484),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { .frequency = CPUFREQ_TABLE_END }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #undef OP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define _BANIAS(cpuid, max, name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { .cpu_id = cpuid, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .max_freq = (max)*1000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .op_points = banias_##max, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* CPU models, their operating frequency range, and freq/voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) operating points */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static struct cpu_model models[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) BANIAS(1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) BANIAS(1100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) BANIAS(1200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) BANIAS(1300),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) BANIAS(1400),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) BANIAS(1500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) BANIAS(1600),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) BANIAS(1700),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* NULL model_name is a wildcard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { NULL, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #undef _BANIAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #undef BANIAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int centrino_cpu_init_table(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct cpu_model *model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) for(model = models; model->cpu_id != NULL; model++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) (model->model_name == NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) strcmp(cpu->x86_model_id, model->model_name) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (model->cpu_id == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* No match at all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pr_debug("no support for CPU model \"%s\": "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "send /proc/cpuinfo to " MAINTAINER "\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) cpu->x86_model_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (model->op_points == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Matched a non-match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pr_debug("no table support for CPU model \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) cpu->x86_model_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pr_debug("try using the acpi-cpufreq driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) per_cpu(centrino_model, policy->cpu) = model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pr_debug("found \"%s\": max frequency: %dkHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) model->model_name, model->max_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static inline int centrino_cpu_init_table(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) const struct cpu_id *x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if ((c->x86 == x->x86) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) (c->x86_model == x->x86_model) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) (c->x86_stepping == x->x86_stepping))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* To be called only after centrino_model is initialized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * Extract clock in kHz from PERF_CTL value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * for centrino, as some DSDTs are buggy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * Ideally, this can be done using the acpi_data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if ((per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_BANIAS]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_A1]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_B0])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) msr = (msr >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return msr * 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if ((!per_cpu(centrino_model, cpu)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) (!per_cpu(centrino_model, cpu)->op_points))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) msr &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) for (i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) per_cpu(centrino_model, cpu)->op_points[i].frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) != CPUFREQ_TABLE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (msr == per_cpu(centrino_model, cpu)->op_points[i].driver_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return per_cpu(centrino_model, cpu)->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) op_points[i].frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (failsafe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return per_cpu(centrino_model, cpu)->op_points[i-1].frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Return the current CPU frequency in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static unsigned int get_cur_freq(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned l, h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned clock_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) rdmsr_on_cpu(cpu, MSR_IA32_PERF_STATUS, &l, &h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) clock_freq = extract_clock(l, cpu, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (unlikely(clock_freq == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * On some CPUs, we can see transient MSR values (which are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * not present in _PSS), while CPU is doing some automatic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * P-state transition (like TM2). Get the last freq set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * in PERF_CTL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) rdmsr_on_cpu(cpu, MSR_IA32_PERF_CTL, &l, &h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) clock_freq = extract_clock(l, cpu, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return clock_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int centrino_cpu_init(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned l, h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Only Intel makes Enhanced Speedstep-capable CPUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (cpu->x86_vendor != X86_VENDOR_INTEL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) !cpu_has(cpu, X86_FEATURE_EST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (policy->cpu != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) for (i = 0; i < N_IDS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (i != N_IDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) per_cpu(centrino_cpu, policy->cpu) = &cpu_ids[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (!per_cpu(centrino_cpu, policy->cpu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pr_debug("found unsupported CPU with "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "Enhanced SpeedStep: send /proc/cpuinfo to "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MAINTAINER "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (centrino_cpu_init_table(policy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Check to see if Enhanced SpeedStep is enabled, and try to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) enable it if not. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) rdmsr(MSR_IA32_MISC_ENABLE, l, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) pr_debug("trying to enable Enhanced SpeedStep (%x)\n", l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) wrmsr(MSR_IA32_MISC_ENABLE, l, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* check to see if it stuck */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) rdmsr(MSR_IA32_MISC_ENABLE, l, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) pr_info("couldn't enable Enhanced SpeedStep\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) policy->cpuinfo.transition_latency = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* 10uS transition latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) policy->freq_table = per_cpu(centrino_model, policy->cpu)->op_points;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int centrino_cpu_exit(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned int cpu = policy->cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!per_cpu(centrino_model, cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) per_cpu(centrino_model, cpu) = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * centrino_target - set a new CPUFreq policy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * @policy: new policy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * @index: index of target frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * Sets a new CPUFreq policy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int centrino_target(struct cpufreq_policy *policy, unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned int j, first_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct cpufreq_frequency_table *op_points;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) cpumask_var_t covered_cpus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (unlikely(!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) retval = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) first_cpu = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) op_points = &per_cpu(centrino_model, cpu)->op_points[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) for_each_cpu(j, policy->cpus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int good_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * Support for SMP systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * Make sure we are running on CPU that wants to change freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) good_cpu = cpumask_any_and(policy->cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) cpu_online_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) good_cpu = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (good_cpu >= nr_cpu_ids) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pr_debug("couldn't limit to CPUs in this domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) retval = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (first_cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* We haven't started the transition yet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) msr = op_points->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (first_cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr, &h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (msr == (oldmsr & 0xffff)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pr_debug("no change needed - msr was and needs "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "to be %x\n", oldmsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) first_cpu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* all but 16 LSB are reserved, treat them with care */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) oldmsr &= ~0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) msr &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) oldmsr |= msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) cpumask_set_cpu(j, covered_cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (unlikely(retval)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * We have failed halfway through the frequency change.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * We have sent callbacks to policy->cpus and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * MSRs have already been written on coverd_cpus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * Best effort undo..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) for_each_cpu(j, covered_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) free_cpumask_var(covered_cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static struct cpufreq_driver centrino_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .name = "centrino", /* should be speedstep-centrino,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) but there's a 16 char limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .init = centrino_cpu_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .exit = centrino_cpu_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .verify = cpufreq_generic_frequency_table_verify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .target_index = centrino_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .get = get_cur_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .attr = cpufreq_generic_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * This doesn't replace the detailed checks above because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * the generic CPU IDs don't have a way to match for steppings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * or ASCII model IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static const struct x86_cpu_id centrino_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, 9, X86_FEATURE_EST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, 13, X86_FEATURE_EST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 15, 3, X86_FEATURE_EST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 15, 4, X86_FEATURE_EST, NULL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * unsupported devices, -ENOENT if there's no voltage table for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * particular CPU model, -EINVAL on problems during initiatization,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * and zero on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * This is quite picky. Not only does the CPU have to advertise the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * "est" flag in the cpuid capability flags, we look for a specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * CPU model and stepping, and we need to have the exact model name in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * our voltage tables. That is, be paranoid about not releasing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * someone's valuable magic smoke.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int __init centrino_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (!x86_match_cpu(centrino_ids))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return cpufreq_register_driver(¢rino_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static void __exit centrino_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) cpufreq_unregister_driver(¢rino_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) MODULE_LICENSE ("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) late_initcall(centrino_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) module_exit(centrino_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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