^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-sa1100/cpu-sa1110.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2001 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Note: there are two erratas that apply to the SA1110 here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * 7 - SDRAM auto-power-up failure (rev A0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 13 - Corruption of internal register reads/writes following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * SDRAM reads (rev A0, B0, B1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * We ignore rev. A0 and B0 devices; I don't think they're worth supporting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/cputype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <mach/generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct sdram_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) const char name[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u_char rows; /* bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u_char cas_latency; /* cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u_char tck; /* clock cycle time (ns) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u_char trcd; /* activate to r/w (ns) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u_char trp; /* precharge to activate (ns) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u_char twr; /* write recovery time (ns) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u_short refresh; /* refresh time for array (us) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct sdram_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u_int mdcnfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u_int mdrefr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u_int mdcas[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static struct sdram_params sdram_tbl[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { /* Toshiba TC59SM716 CL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .name = "TC59SM716-CL2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .rows = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .tck = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .trcd = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .trp = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .twr = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .refresh = 64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .cas_latency = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }, { /* Toshiba TC59SM716 CL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .name = "TC59SM716-CL3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .rows = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .tck = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .trcd = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .trp = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .twr = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .refresh = 64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .cas_latency = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }, { /* Samsung K4S641632D TC75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .name = "K4S641632D",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .rows = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .tck = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .trcd = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .trp = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .twr = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .refresh = 64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .cas_latency = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }, { /* Samsung K4S281632B-1H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .name = "K4S281632B-1H",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .rows = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .tck = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .trp = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .twr = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .refresh = 64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .cas_latency = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }, { /* Samsung KM416S4030CT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .name = "KM416S4030CT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .rows = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .tck = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .trcd = 24, /* 3 CLKs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .trp = 24, /* 3 CLKs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .twr = 16, /* Trdl: 2 CLKs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .refresh = 64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .cas_latency = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }, { /* Winbond W982516AH75L CL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .name = "W982516AH75L",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .rows = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .tck = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .trcd = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .trp = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .twr = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .refresh = 64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .cas_latency = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }, { /* Micron MT48LC8M16A2TG-75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .name = "MT48LC8M16A2TG-75",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .rows = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .tck = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .trcd = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .trp = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .twr = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .refresh = 64000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .cas_latency = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct sdram_params sdram_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Given a period in ns and frequency in khz, calculate the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * cycles of frequency in period. Note that we round up to the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * cycle, even if we are only slightly over.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline u_int ns_to_cycles(u_int ns, u_int khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return (ns * khz + 999999) / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Create the MDCAS register bit pattern.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static inline void set_mdcas(u_int *mdcas, int delayed, u_int rcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u_int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) rcd = 2 * rcd - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) shift = delayed + 1 + rcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mdcas[0] = (1 << rcd) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mdcas[0] |= 0x55555555 << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mdcas[1] = mdcas[2] = 0x55555555 << (shift & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) sdram_calculate_timing(struct sdram_info *sd, u_int cpu_khz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct sdram_params *sdram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u_int mem_khz, sd_khz, trp, twr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mem_khz = cpu_khz / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) sd_khz = mem_khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * If SDCLK would invalidate the SDRAM timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * run SDCLK at half speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * CPU steppings prior to B2 must either run the memory at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * half speed or use delayed read latching (errata 13).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if ((ns_to_cycles(sdram->tck, sd_khz) > 1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) (read_cpuid_revision() < ARM_CPU_REV_SA1110_B2 && sd_khz < 62000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) sd_khz /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) sd->mdcnfg = MDCNFG & 0x007f007f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) twr = ns_to_cycles(sdram->twr, mem_khz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* trp should always be >1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) trp = ns_to_cycles(sdram->trp, mem_khz) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (trp < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) trp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) sd->mdcnfg |= trp << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) sd->mdcnfg |= trp << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) sd->mdcnfg |= sdram->cas_latency << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) sd->mdcnfg |= sdram->cas_latency << 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) sd->mdcnfg |= twr << 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) sd->mdcnfg |= twr << 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) sd->mdrefr = MDREFR & 0xffbffff0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) sd->mdrefr |= 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (sd_khz != mem_khz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) sd->mdrefr |= MDREFR_K1DB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* initial number of '1's in MDCAS + 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) set_mdcas(sd->mdcas, sd_khz >= 62000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ns_to_cycles(sdram->trcd, mem_khz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) printk(KERN_DEBUG "MDCNFG: %08x MDREFR: %08x MDCAS0: %08x MDCAS1: %08x MDCAS2: %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) sd->mdcnfg, sd->mdrefr, sd->mdcas[0], sd->mdcas[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) sd->mdcas[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * Set the SDRAM refresh rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static inline void sdram_set_refresh(u_int dri)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MDREFR = (MDREFR & 0xffff000f) | (dri << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) (void) MDREFR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Update the refresh period. We do this such that we always refresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * the SDRAMs within their permissible period. The refresh period is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * always a multiple of the memory clock (fixed at cpu_clock / 2).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * FIXME: we don't currently take account of burst accesses here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * but neither do Intels DM nor Angel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) sdram_update_refresh(u_int cpu_khz, struct sdram_params *sdram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u_int ns_row = (sdram->refresh * 1000) >> sdram->rows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u_int dri = ns_to_cycles(ns_row, cpu_khz / 2) / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mdelay(250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) printk(KERN_DEBUG "new dri value = %d\n", dri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) sdram_set_refresh(dri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Ok, set the CPU frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int sa1110_target(struct cpufreq_policy *policy, unsigned int ppcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct sdram_params *sdram = &sdram_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct sdram_info sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned int unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) sdram_calculate_timing(&sd, sa11x0_freq_table[ppcr].frequency, sdram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * These values are wrong according to the SA1110 documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * and errata, but they seem to work. Need to get a storage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * scope on to the SDRAM signals to work out why.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (policy->max < 147500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) sd.mdrefr |= MDREFR_K1DB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) sd.mdcas[0] = 0xaaaaaa7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) sd.mdrefr &= ~MDREFR_K1DB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) sd.mdcas[0] = 0xaaaaaa9f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) sd.mdcas[1] = 0xaaaaaaaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) sd.mdcas[2] = 0xaaaaaaaa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * The clock could be going away for some time. Set the SDRAMs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * to refresh rapidly (every 64 memory clock cycles). To get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * through the whole array, we need to wait 262144 mclk cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * We wait 20ms to be safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) sdram_set_refresh(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!irqs_disabled())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mdelay(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * Reprogram the DRAM timings with interrupts disabled, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * ensure that we are doing this within a complete cache line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * This means that we won't access SDRAM for the duration of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * the programming.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) __asm__ __volatile__("\n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) b 2f \n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .align 5 \n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 1: str %3, [%1, #0] @ MDCNFG \n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) str %4, [%1, #28] @ MDREFR \n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) str %5, [%1, #4] @ MDCAS0 \n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) str %6, [%1, #8] @ MDCAS1 \n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) str %7, [%1, #12] @ MDCAS2 \n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) str %8, [%2, #0] @ PPCR \n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ldr %0, [%1, #0] \n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) b 3f \n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 2: b 1b \n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 3: nop \n\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) nop"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) : "=&r" (unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) : "r" (&MDCNFG), "r" (&PPCR), "0" (sd.mdcnfg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "r" (sd.mdrefr), "r" (sd.mdcas[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "r" (sd.mdcas[1]), "r" (sd.mdcas[2]), "r" (ppcr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * Now, return the SDRAM refresh back to normal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) sdram_update_refresh(sa11x0_freq_table[ppcr].frequency, sdram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int __init sa1110_cpu_init(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) cpufreq_generic_init(policy, sa11x0_freq_table, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* sa1110_driver needs __refdata because it must remain after init registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * it with cpufreq_register_driver() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static struct cpufreq_driver sa1110_driver __refdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .verify = cpufreq_generic_frequency_table_verify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .target_index = sa1110_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .get = sa11x0_getspeed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .init = sa1110_cpu_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .name = "sa1110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static struct sdram_params *sa1110_find_sdram(const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct sdram_params *sdram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) for (sdram = sdram_tbl; sdram < sdram_tbl + ARRAY_SIZE(sdram_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) sdram++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (strcmp(name, sdram->name) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return sdram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static char sdram_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int __init sa1110_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct sdram_params *sdram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) const char *name = sdram_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!cpu_is_sa1110())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!name[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (machine_is_assabet())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) name = "TC59SM716-CL3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (machine_is_pt_system3())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) name = "K4S641632D";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (machine_is_h3100())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) name = "KM416S4030CT";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (machine_is_jornada720() || machine_is_h3600())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) name = "K4S281632B-1H";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (machine_is_nanoengine())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) name = "MT48LC8M16A2TG-75";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) sdram = sa1110_find_sdram(name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (sdram) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) " twr: %d refresh: %d cas_latency: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) sdram->tck, sdram->trcd, sdram->trp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) sdram->twr, sdram->refresh, sdram->cas_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) memcpy(&sdram_params, sdram, sizeof(sdram_params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return cpufreq_register_driver(&sa1110_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) module_param_string(sdram, sdram_name, sizeof(sdram_name), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) arch_initcall(sa1110_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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