^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2010 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * CPU frequency scaling for S5PC110/S5PV210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static void __iomem *clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static void __iomem *dmc_base[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S5P_CLKREG(x) (clk_base + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define S5P_APLL_LOCK S5P_CLKREG(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S5P_APLL_CON S5P_CLKREG(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S5P_CLK_SRC0 S5P_CLKREG(0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S5P_CLK_SRC2 S5P_CLKREG(0x208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S5P_CLK_DIV0 S5P_CLKREG(0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define S5P_CLK_DIV2 S5P_CLKREG(0x308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S5P_CLK_DIV6 S5P_CLKREG(0x318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S5P_ARM_MCS_CON S5P_CLKREG(0x6100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* CLKSRC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S5P_CLKSRC0_MUX200_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S5P_CLKSRC0_MUX166_MASK (0x1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S5P_CLKSRC0_MUX133_MASK (0x1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* CLKSRC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S5P_CLKSRC2_G3D_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define S5P_CLKSRC2_G3D_MASK (0x3 << S5P_CLKSRC2_G3D_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define S5P_CLKSRC2_MFC_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define S5P_CLKSRC2_MFC_MASK (0x3 << S5P_CLKSRC2_MFC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* CLKDIV0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define S5P_CLKDIV0_APLL_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define S5P_CLKDIV0_A2M_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define S5P_CLKDIV0_HCLK200_SHIFT (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define S5P_CLKDIV0_HCLK200_MASK (0x7 << S5P_CLKDIV0_HCLK200_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define S5P_CLKDIV0_PCLK100_SHIFT (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S5P_CLKDIV0_PCLK100_MASK (0x7 << S5P_CLKDIV0_PCLK100_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define S5P_CLKDIV0_HCLK166_SHIFT (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define S5P_CLKDIV0_HCLK166_MASK (0xF << S5P_CLKDIV0_HCLK166_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define S5P_CLKDIV0_PCLK83_SHIFT (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define S5P_CLKDIV0_PCLK83_MASK (0x7 << S5P_CLKDIV0_PCLK83_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define S5P_CLKDIV0_HCLK133_SHIFT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define S5P_CLKDIV0_HCLK133_MASK (0xF << S5P_CLKDIV0_HCLK133_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define S5P_CLKDIV0_PCLK66_SHIFT (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* CLKDIV2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define S5P_CLKDIV2_G3D_SHIFT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define S5P_CLKDIV2_G3D_MASK (0xF << S5P_CLKDIV2_G3D_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define S5P_CLKDIV2_MFC_SHIFT (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define S5P_CLKDIV2_MFC_MASK (0xF << S5P_CLKDIV2_MFC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* CLKDIV6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define S5P_CLKDIV6_ONEDRAM_SHIFT (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define S5P_CLKDIV6_ONEDRAM_MASK (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static struct clk *dmc0_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static struct clk *dmc1_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static DEFINE_MUTEX(set_freq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* APLL M,P,S values for 1G/800Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Use 800MHz when entering sleep mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SLEEP_FREQ (800 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Tracks if cpu freqency can be updated anymore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static bool no_cpufreq_access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * DRAM configurations to calculate refresh counter for changing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * frequency of memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct dram_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned long freq; /* HZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long refresh; /* DRAM refresh counter * 1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* DRAM configuration (DMC0 and DMC1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static struct dram_conf s5pv210_dram_conf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) enum perf_level {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) L0, L1, L2, L3, L4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enum s5pv210_mem_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) LPDDR = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) LPDDR2 = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DDR2 = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) enum s5pv210_dmc_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DMC0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) DMC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct cpufreq_frequency_table s5pv210_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {0, L0, 1000*1000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {0, L1, 800*1000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {0, L2, 400*1000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {0, L3, 200*1000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {0, L4, 100*1000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {0, 0, CPUFREQ_TABLE_END},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct regulator *arm_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static struct regulator *int_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct s5pv210_dvs_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int arm_volt; /* uV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int int_volt; /* uV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const int arm_volt_max = 1350000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const int int_volt_max = 1250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct s5pv210_dvs_conf dvs_conf[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [L0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .arm_volt = 1250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .int_volt = 1100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) [L1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .arm_volt = 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .int_volt = 1100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [L2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .arm_volt = 1050000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .int_volt = 1100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [L3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .arm_volt = 950000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .int_volt = 1100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [L4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .arm_volt = 950000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .int_volt = 1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static u32 clkdiv_val[5][11] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Clock divider value for following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * ONEDRAM, MFC, G3D }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* L0 : [1000/200/100][166/83][133/66][200/200] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* L1 : [800/200/100][166/83][133/66][200/200] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* L2 : [400/200/100][166/83][133/66][200/200] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* L3 : [200/200/100][166/83][133/66][200/200] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* L4 : [100/100/100][83/83][66/66][100/100] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * This function set DRAM refresh counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * accoriding to operating frequency of DRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * ch: DMC port number 0 or 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * freq: Operating frequency of DRAM(KHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned long tmp, tmp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) void __iomem *reg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (ch == DMC0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) reg = (dmc_base[0] + 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) } else if (ch == DMC1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) reg = (dmc_base[1] + 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pr_err("Cannot find DMC port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Find current DRAM frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) tmp = s5pv210_dram_conf[ch].freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) tmp /= freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) tmp1 = s5pv210_dram_conf[ch].refresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) tmp1 /= tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writel_relaxed(tmp1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int priv_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int pll_changing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned int bus_speed_changing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned int old_freq, new_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int arm_volt, int_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mutex_lock(&set_freq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (no_cpufreq_access) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pr_err("Denied access to %s as it is disabled temporarily\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) old_freq = policy->cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) new_freq = s5pv210_freq_table[index].frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Finding current running level index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) priv_index = cpufreq_table_find_index_h(policy, old_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) arm_volt = dvs_conf[index].arm_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int_volt = dvs_conf[index].int_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (new_freq > old_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = regulator_set_voltage(arm_regulator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) arm_volt, arm_volt_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = regulator_set_voltage(int_regulator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int_volt, int_volt_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Check if there need to change PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if ((index == L0) || (priv_index == L0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pll_changing = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* Check if there need to change System bus clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if ((index == L4) || (priv_index == L4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) bus_speed_changing = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (bus_speed_changing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * Reconfigure DRAM refresh counter value for minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * temporary clock while changing divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (pll_changing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) s5pv210_set_refresh(DMC1, 83000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) s5pv210_set_refresh(DMC1, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) s5pv210_set_refresh(DMC0, 83000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * APLL should be changed in this level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * APLL -> MPLL(for stable transition) -> APLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * Some clock source's clock API are not prepared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Do not use clock API in below code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (pll_changing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * 1. Temporary Change divider for MFC and G3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * SCLKA2M(200/1=200)->(200/4=50)Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) reg = readl_relaxed(S5P_CLK_DIV2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) (3 << S5P_CLKDIV2_MFC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) writel_relaxed(reg, S5P_CLK_DIV2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* For MFC, G3D dividing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) reg = readl_relaxed(S5P_CLKDIV_STAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } while (reg & ((1 << 16) | (1 << 17)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * (200/4=50)->(667/4=166)Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) reg = readl_relaxed(S5P_CLK_SRC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) (1 << S5P_CLKSRC2_MFC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) writel_relaxed(reg, S5P_CLK_SRC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) reg = readl_relaxed(S5P_CLKMUX_STAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) } while (reg & ((1 << 7) | (1 << 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * 3. DMC1 refresh count for 133Mhz if (index == L4) is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * true refresh counter is already programed in upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * code. 0x287@83Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!bus_speed_changing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) s5pv210_set_refresh(DMC1, 133000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* 4. SCLKAPLL -> SCLKMPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) reg = readl_relaxed(S5P_CLK_SRC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) reg &= ~(S5P_CLKSRC0_MUX200_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) writel_relaxed(reg, S5P_CLK_SRC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) reg = readl_relaxed(S5P_CLKMUX_STAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } while (reg & (0x1 << 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Change divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) reg = readl_relaxed(S5P_CLK_DIV0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) writel_relaxed(reg, S5P_CLK_DIV0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) reg = readl_relaxed(S5P_CLKDIV_STAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) } while (reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* ARM MCS value changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) reg = readl_relaxed(S5P_ARM_MCS_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) reg &= ~0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (index >= L3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) reg |= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) reg |= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) writel_relaxed(reg, S5P_ARM_MCS_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (pll_changing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) writel_relaxed(0x2cf, S5P_APLL_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * 6. Turn on APLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * 6-1. Set PMS values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * 6-2. Wait untile the PLL is locked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (index == L0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) writel_relaxed(APLL_VAL_1000, S5P_APLL_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) writel_relaxed(APLL_VAL_800, S5P_APLL_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) reg = readl_relaxed(S5P_APLL_CON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) } while (!(reg & (0x1 << 29)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * 7. Change souce clock from SCLKMPLL(667Mhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * (667/4=166)->(200/4=50)Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) reg = readl_relaxed(S5P_CLK_SRC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) (0 << S5P_CLKSRC2_MFC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) writel_relaxed(reg, S5P_CLK_SRC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) reg = readl_relaxed(S5P_CLKMUX_STAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) } while (reg & ((1 << 7) | (1 << 3)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * 8. Change divider for MFC and G3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * (200/4=50)->(200/1=200)Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) reg = readl_relaxed(S5P_CLK_DIV2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) writel_relaxed(reg, S5P_CLK_DIV2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* For MFC, G3D dividing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) reg = readl_relaxed(S5P_CLKDIV_STAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) } while (reg & ((1 << 16) | (1 << 17)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* 9. Change MPLL to APLL in MSYS_MUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) reg = readl_relaxed(S5P_CLK_SRC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) reg &= ~(S5P_CLKSRC0_MUX200_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) writel_relaxed(reg, S5P_CLK_SRC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) reg = readl_relaxed(S5P_CLKMUX_STAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) } while (reg & (0x1 << 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * 10. DMC1 refresh counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!bus_speed_changing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) s5pv210_set_refresh(DMC1, 200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * L4 level need to change memory bus speed, hence onedram clock divier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * and memory refresh parameter should be changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (bus_speed_changing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) reg = readl_relaxed(S5P_CLK_DIV6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) writel_relaxed(reg, S5P_CLK_DIV6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) reg = readl_relaxed(S5P_CLKDIV_STAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) } while (reg & (1 << 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* Reconfigure DRAM refresh counter value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (index != L4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * DMC0 : 166Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * DMC1 : 200Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) s5pv210_set_refresh(DMC0, 166000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) s5pv210_set_refresh(DMC1, 200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * DMC0 : 83Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * DMC1 : 100Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) s5pv210_set_refresh(DMC0, 83000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) s5pv210_set_refresh(DMC1, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (new_freq < old_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) regulator_set_voltage(int_regulator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int_volt, int_volt_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) regulator_set_voltage(arm_regulator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) arm_volt, arm_volt_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pr_debug("Perf changed[L%d]\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) mutex_unlock(&set_freq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int check_mem_type(void __iomem *dmc_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) val = readl_relaxed(dmc_reg + 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) val = (val & (0xf << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return val >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int s5pv210_cpu_init(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) unsigned long mem_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) policy->clk = clk_get(NULL, "armclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (IS_ERR(policy->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return PTR_ERR(policy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dmc0_clk = clk_get(NULL, "sclk_dmc0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (IS_ERR(dmc0_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret = PTR_ERR(dmc0_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) goto out_dmc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) dmc1_clk = clk_get(NULL, "hclk_msys");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (IS_ERR(dmc1_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) ret = PTR_ERR(dmc1_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) goto out_dmc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (policy->cpu != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) goto out_dmc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * check_mem_type : This driver only support LPDDR & LPDDR2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * other memory type is not supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) mem_type = check_mem_type(dmc_base[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pr_err("CPUFreq doesn't support this memory type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) goto out_dmc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Find current refresh counter and frequency each DMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) s5pv210_dram_conf[0].refresh = (readl_relaxed(dmc_base[0] + 0x30) * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) s5pv210_dram_conf[1].refresh = (readl_relaxed(dmc_base[1] + 0x30) * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) policy->suspend_freq = SLEEP_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) cpufreq_generic_init(policy, s5pv210_freq_table, 40000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) out_dmc1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) clk_put(dmc0_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) out_dmc0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) clk_put(policy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned long event, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct cpufreq_policy *policy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) policy = cpufreq_cpu_get(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!policy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pr_debug("cpufreq: get no policy for cpu0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = cpufreq_driver_target(policy, SLEEP_FREQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) cpufreq_cpu_put(policy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) no_cpufreq_access = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static struct cpufreq_driver s5pv210_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .verify = cpufreq_generic_frequency_table_verify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .target_index = s5pv210_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .get = cpufreq_generic_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .init = s5pv210_cpu_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .name = "s5pv210",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .suspend = cpufreq_generic_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .resume = cpufreq_generic_suspend, /* We need to set SLEEP FREQ again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static struct notifier_block s5pv210_cpufreq_reboot_notifier = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .notifier_call = s5pv210_cpufreq_reboot_notifier_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int s5pv210_cpufreq_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int id, result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * HACK: This is a temporary workaround to get access to clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * and DMC controller registers directly and remove static mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * and dependencies on platform headers. It is necessary to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * S5PV210 multi-platform support and will be removed together with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * this whole driver as soon as S5PV210 gets migrated to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * cpufreq-dt driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) arm_regulator = regulator_get(NULL, "vddarm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (IS_ERR(arm_regulator))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return dev_err_probe(dev, PTR_ERR(arm_regulator),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) "failed to get regulator vddarm\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int_regulator = regulator_get(NULL, "vddint");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (IS_ERR(int_regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) result = dev_err_probe(dev, PTR_ERR(int_regulator),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) "failed to get regulator vddint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) goto err_int_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_err(dev, "failed to find clock controller DT node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) result = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) goto err_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) clk_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!clk_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dev_err(dev, "failed to map clock registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) result = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) goto err_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) for_each_compatible_node(np, NULL, "samsung,s5pv210-dmc") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) id = of_alias_get_id(np, "dmc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (id < 0 || id >= ARRAY_SIZE(dmc_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev_err(dev, "failed to get alias of dmc node '%pOFn'\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) result = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) goto err_clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dmc_base[id] = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (!dmc_base[id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dev_err(dev, "failed to map dmc%d registers\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) result = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) goto err_dmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) for (id = 0; id < ARRAY_SIZE(dmc_base); ++id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (!dmc_base[id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev_err(dev, "failed to find dmc%d node\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) result = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) goto err_dmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) register_reboot_notifier(&s5pv210_cpufreq_reboot_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return cpufreq_register_driver(&s5pv210_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) err_dmc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) for (id = 0; id < ARRAY_SIZE(dmc_base); ++id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (dmc_base[id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) iounmap(dmc_base[id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dmc_base[id] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) err_clk_base:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) iounmap(clk_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) err_clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) regulator_put(int_regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) err_int_regulator:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) regulator_put(arm_regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static struct platform_driver s5pv210_cpufreq_platdrv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .name = "s5pv210-cpufreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .probe = s5pv210_cpufreq_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) builtin_platform_driver(s5pv210_cpufreq_platdrv);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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