^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2009 Wolfson Microelectronics plc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * S3C64xx CPUfreq Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define pr_fmt(fmt) "cpufreq: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static struct regulator *vddarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static unsigned long regulator_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct s3c64xx_dvfs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int vddarm_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) unsigned int vddarm_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) [0] = { 1000000, 1150000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) [1] = { 1050000, 1150000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) [2] = { 1100000, 1150000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) [3] = { 1200000, 1350000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) [4] = { 1300000, 1350000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { 0, 0, 66000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { 0, 0, 100000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { 0, 0, 133000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { 0, 1, 200000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { 0, 1, 222000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { 0, 1, 266000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { 0, 2, 333000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { 0, 2, 400000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { 0, 2, 532000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { 0, 2, 533000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { 0, 3, 667000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { 0, 4, 800000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { 0, 0, CPUFREQ_TABLE_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct s3c64xx_dvfs *dvfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int old_freq, new_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) old_freq = clk_get_rate(policy->clk) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) new_freq = s3c64xx_freq_table[index].frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[index].driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #ifdef CONFIG_REGULATOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (vddarm && new_freq > old_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ret = regulator_set_voltage(vddarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) dvfs->vddarm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) dvfs->vddarm_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pr_err("Failed to set VDDARM for %dkHz: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) new_freq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ret = clk_set_rate(policy->clk, new_freq * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pr_err("Failed to set rate %dkHz: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) new_freq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #ifdef CONFIG_REGULATOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (vddarm && new_freq < old_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = regulator_set_voltage(vddarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) dvfs->vddarm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dvfs->vddarm_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pr_err("Failed to set VDDARM for %dkHz: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) new_freq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (clk_set_rate(policy->clk, old_freq * 1000) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pr_err("Failed to restore original clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pr_debug("Set actual frequency %lukHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clk_get_rate(policy->clk) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #ifdef CONFIG_REGULATOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void s3c64xx_cpufreq_config_regulator(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int count, v, i, found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct cpufreq_frequency_table *freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct s3c64xx_dvfs *dvfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) count = regulator_count_voltages(vddarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (count < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pr_err("Unable to check supported voltages\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) cpufreq_for_each_valid_entry(freq, s3c64xx_freq_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dvfs = &s3c64xx_dvfs_table[freq->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) v = regulator_list_voltage(vddarm, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (!found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pr_debug("%dkHz unsupported by regulator\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) freq->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) freq->frequency = CPUFREQ_ENTRY_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Guess based on having to do an I2C/SPI write; in future we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * will be able to query the regulator performance here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) regulator_latency = 1 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct cpufreq_frequency_table *freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (policy->cpu != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) policy->clk = clk_get(NULL, "armclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (IS_ERR(policy->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pr_err("Unable to obtain ARMCLK: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PTR_ERR(policy->clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return PTR_ERR(policy->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #ifdef CONFIG_REGULATOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) vddarm = regulator_get(NULL, "vddarm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (IS_ERR(vddarm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) pr_err("Failed to obtain VDDARM: %ld\n", PTR_ERR(vddarm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pr_err("Only frequency scaling available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) vddarm = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) s3c64xx_cpufreq_config_regulator();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) cpufreq_for_each_entry(freq, s3c64xx_freq_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned long r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Check for frequencies we can generate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) r = clk_round_rate(policy->clk, freq->frequency * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) r /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (r != freq->frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pr_debug("%dkHz unsupported by clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) freq->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) freq->frequency = CPUFREQ_ENTRY_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* If we have no regulator then assume startup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * frequency is the maximum we can support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!vddarm && freq->frequency > clk_get_rate(policy->clk) / 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) freq->frequency = CPUFREQ_ENTRY_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Datasheet says PLL stabalisation time (if we were to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * the PLLs, which we don't currently) is ~300us worst case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * but add some fudge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) cpufreq_generic_init(policy, s3c64xx_freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) (500 * 1000) + regulator_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct cpufreq_driver s3c64xx_cpufreq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .verify = cpufreq_generic_frequency_table_verify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .target_index = s3c64xx_cpufreq_set_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .get = cpufreq_generic_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .init = s3c64xx_cpufreq_driver_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .name = "s3c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int __init s3c64xx_cpufreq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) module_init(s3c64xx_cpufreq_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags