^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2006-2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * S3C24XX CPU Frequency scaling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/soc/samsung/s3c-cpufreq-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/soc/samsung/s3c-pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* note, cpufreq support deals in kHz, no Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static struct cpufreq_driver s3c24xx_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct s3c_cpufreq_config cpu_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct s3c_iotimings s3c24xx_iotiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static struct cpufreq_frequency_table *pll_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static unsigned int last_target = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static unsigned int ftab_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static struct cpufreq_frequency_table *ftab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static struct clk *_clk_mpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct clk *_clk_xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static struct clk *clk_fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static struct clk *clk_hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static struct clk *clk_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct clk *clk_arm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return &cpu_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct s3c_iotimings *s3c_cpufreq_getiotimings(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return &s3c24xx_iotiming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned long fclk, pclk, hclk, armclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) cfg->freq.fclk = fclk = clk_get_rate(clk_fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) cfg->freq.hclk = hclk = clk_get_rate(clk_hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) cfg->freq.pclk = pclk = clk_get_rate(clk_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) cfg->freq.armclk = armclk = clk_get_rate(clk_arm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) cfg->pll.driver_data = s3c24xx_read_mpllcon();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) cfg->pll.frequency = fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) cfg->divs.h_divisor = fclk / hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) cfg->divs.p_divisor = fclk / pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long pll = cfg->pll.frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) cfg->freq.fclk = pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) cfg->freq.hclk = pll / cfg->divs.h_divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) cfg->freq.pclk = pll / cfg->divs.p_divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* convert hclk into 10ths of nanoseconds for io calcs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline int closer(unsigned int target, unsigned int n, unsigned int c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int diff_cur = abs(target - c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int diff_new = abs(target - n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return (diff_new < diff_cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void s3c_cpufreq_show(const char *pfx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct s3c_cpufreq_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) cfg->freq.hclk, cfg->divs.h_divisor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) cfg->freq.pclk, cfg->divs.p_divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* functions to wrapper the driver info calls to do the cpu specific work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (cfg->info->set_iotiming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (cfg->info->calc_iotiming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) (cfg->info->set_refresh)(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) (cfg->info->set_divs)(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return (cfg->info->calc_divs)(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) cfg->mpll = _clk_mpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) (cfg->info->set_fvco)(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline void s3c_cpufreq_updateclk(struct clk *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) clk_set_rate(clk, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int s3c_cpufreq_settarget(struct cpufreq_policy *policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int target_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct cpufreq_frequency_table *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct s3c_cpufreq_freqs freqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct s3c_cpufreq_config cpu_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cpu_new = cpu_cur; /* copy new from current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) s3c_cpufreq_show("cur", &cpu_cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* TODO - check for DMA currently outstanding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) cpu_new.pll = pll ? *pll : cpu_cur.pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) freqs.pll_changing = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* update our frequencies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) cpu_new.freq.armclk = target_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) cpu_new.freq.fclk = cpu_new.pll.frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (s3c_cpufreq_calcdivs(&cpu_new) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pr_err("no divisors for %d\n", target_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) goto err_notpossible;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) s3c_freq_dbg("%s: got divs\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) s3c_cpufreq_calc(&cpu_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) s3c_freq_dbg("%s: calculated frequencies for new\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (cpu_new.freq.hclk != cpu_cur.freq.hclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (s3c_cpufreq_calcio(&cpu_new) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pr_err("%s: no IO timings\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) goto err_notpossible;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) s3c_cpufreq_show("new", &cpu_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* setup our cpufreq parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) freqs.old = cpu_cur.freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) freqs.new = cpu_new.freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) freqs.freqs.old = cpu_cur.freq.armclk / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) freqs.freqs.new = cpu_new.freq.armclk / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* update f/h/p clock settings before we issue the change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * notification, so that drivers do not need to do anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * special if they want to recalculate on CPUFREQ_PRECHANGE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* start the frequency change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) cpufreq_freq_transition_begin(policy, &freqs.freqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* If hclk is staying the same, then we do not need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * re-write the IO or the refresh timings whilst we are changing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * speed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* is our memory clock slowing down? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (cpu_new.freq.hclk < cpu_cur.freq.hclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) s3c_cpufreq_setrefresh(&cpu_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) s3c_cpufreq_setio(&cpu_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (cpu_new.freq.fclk == cpu_cur.freq.fclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* not changing PLL, just set the divisors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) s3c_cpufreq_setdivs(&cpu_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (cpu_new.freq.fclk < cpu_cur.freq.fclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* slow the cpu down, then set divisors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) s3c_cpufreq_setfvco(&cpu_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) s3c_cpufreq_setdivs(&cpu_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* set the divisors, then speed up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) s3c_cpufreq_setdivs(&cpu_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) s3c_cpufreq_setfvco(&cpu_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* did our memory clock speed up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (cpu_new.freq.hclk > cpu_cur.freq.hclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) s3c_cpufreq_setrefresh(&cpu_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) s3c_cpufreq_setio(&cpu_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* update our current settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) cpu_cur = cpu_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* notify everyone we've done this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) cpufreq_freq_transition_end(policy, &freqs.freqs, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) s3c_freq_dbg("%s: finished\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) err_notpossible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pr_err("no compatible settings for %d\n", target_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* s3c_cpufreq_target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * called by the cpufreq core to adjust the frequency that the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * is currently running at.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int s3c_cpufreq_target(struct cpufreq_policy *policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned int target_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int relation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct cpufreq_frequency_table *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* avoid repeated calls which cause a needless amout of duplicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * logging output (and CPU time as the calculation process is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * done) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (target_freq == last_target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) last_target = target_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) s3c_freq_dbg("%s: policy %p, target %u, relation %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) __func__, policy, target_freq, relation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (ftab) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) index = cpufreq_frequency_table_target(policy, target_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) relation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) target_freq, index, ftab[index].frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) target_freq = ftab[index].frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) target_freq *= 1000; /* convert target to Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* find the settings for our new frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (!pll_reg || cpu_cur.lock_pll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* either we've not got any PLL values, or we've locked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * to the current one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pll = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct cpufreq_policy tmp_policy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* we keep the cpu pll table in Hz, to ensure we get an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * accurate value for the PLL output. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) tmp_policy.min = policy->min * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) tmp_policy.max = policy->max * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) tmp_policy.cpu = policy->cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) tmp_policy.freq_table = pll_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* cpufreq_frequency_table_target returns the index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * of the table entry, not the value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * the table entry's index field. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) index = cpufreq_frequency_table_target(&tmp_policy, target_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) relation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) pll = pll_reg + index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) s3c_freq_dbg("%s: target %u => %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) __func__, target_freq, pll->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) target_freq = pll->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return s3c_cpufreq_settarget(policy, target_freq, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) clk = clk_get(dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pr_err("failed to get clock '%s'\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int s3c_cpufreq_init(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) policy->clk = clk_arm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) policy->cpuinfo.transition_latency = cpu_cur.info->latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) policy->freq_table = ftab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static int __init s3c_cpufreq_initclks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) clk_arm = s3c_cpufreq_clk_get(NULL, "armclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) pr_err("%s: could not get clock(s)\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pr_info("%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) clk_get_rate(clk_fclk) / 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) clk_get_rate(clk_hclk) / 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) clk_get_rate(clk_pclk) / 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) clk_get_rate(clk_arm) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct cpufreq_frequency_table suspend_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static unsigned int suspend_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int s3c_cpufreq_suspend(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) suspend_pll.frequency = clk_get_rate(_clk_mpll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) suspend_pll.driver_data = s3c24xx_read_mpllcon();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) suspend_freq = clk_get_rate(clk_arm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int s3c_cpufreq_resume(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) last_target = ~0; /* invalidate last_target setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* whilst we will be called later on, we try and re-set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * cpu frequencies as soon as possible so that we do not end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * up resuming devices and then immediately having to re-set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * a number of settings once these devices have restarted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * as a note, it is expected devices are not used until they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * have been un-suspended and at that time they should have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * used the updated clock settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) pr_err("%s: failed to reset pll/freq\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define s3c_cpufreq_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define s3c_cpufreq_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static struct cpufreq_driver s3c24xx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .target = s3c_cpufreq_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .get = cpufreq_generic_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .init = s3c_cpufreq_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .suspend = s3c_cpufreq_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .resume = s3c_cpufreq_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .name = "s3c24xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int s3c_cpufreq_register(struct s3c_cpufreq_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (!info || !info->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) pr_err("%s: failed to pass valid information\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pr_info("S3C24XX CPU Frequency driver, %s cpu support\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) info->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* check our driver info has valid data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) BUG_ON(info->set_refresh == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) BUG_ON(info->set_divs == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) BUG_ON(info->calc_divs == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* info->set_fvco is optional, depending on whether there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * is a need to set the clock code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) cpu_cur.info = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Note, driver registering should probably update locktime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct s3c_cpufreq_board *ours;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!board) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pr_info("%s: no board data\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Copy the board information so that each board can make this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * initdata. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ours = kzalloc(sizeof(*ours), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (!ours)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) *ours = *board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) cpu_cur.board = ours;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int __init s3c_cpufreq_auto_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (!cpu_cur.info->get_iotiming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) pr_err("%s: get_iotiming undefined\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pr_info("%s: working out IO settings\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) pr_err("%s: failed to get timings\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* if one or is zero, then return the other, otherwise return the min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * s3c_cpufreq_freq_min - find the minimum settings for the given freq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * @dst: The destination structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * @a: One argument.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * @b: The other argument.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * Create a minimum of each frequency entry in the 'struct s3c_freq',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * unless the entry is zero when it is ignored and the non-zero argument
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static void s3c_cpufreq_freq_min(struct s3c_freq *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct s3c_freq *a, struct s3c_freq *b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dst->fclk = do_min(a->fclk, b->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dst->hclk = do_min(a->hclk, b->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dst->pclk = do_min(a->pclk, b->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dst->armclk = do_min(a->armclk, b->armclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static inline u32 calc_locktime(u32 freq, u32 time_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) result = freq * time_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) result = DIV_ROUND_UP(result, 1000 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void s3c_cpufreq_update_loctkime(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned int bits = cpu_cur.info->locktime_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 rate = (u32)clk_get_rate(_clk_xtal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (bits == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) val |= calc_locktime(rate, cpu_cur.info->locktime_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pr_info("%s: new locktime is 0x%08x\n", __func__, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) s3c24xx_write_locktime(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int s3c_cpufreq_build_freq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int size, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) kfree(ftab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) size++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ftab = kcalloc(size, sizeof(*ftab), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (!ftab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ftab_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int __init s3c_cpufreq_initcall(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (cpu_cur.info && cpu_cur.board) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = s3c_cpufreq_initclks();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* get current settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) s3c_cpufreq_getcur(&cpu_cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) s3c_cpufreq_show("cur", &cpu_cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (cpu_cur.board->auto_io) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = s3c_cpufreq_auto_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pr_err("%s: failed to get io timing\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pr_err("%s: no IO support registered\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (!cpu_cur.info->need_pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) cpu_cur.lock_pll = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) s3c_cpufreq_update_loctkime();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) &cpu_cur.info->max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (cpu_cur.info->calc_freqtable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) s3c_cpufreq_build_freq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ret = cpufreq_register_driver(&s3c24xx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) late_initcall(s3c_cpufreq_initcall);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * s3c_plltab_register - register CPU PLL table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * @plls: The list of PLL entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * @plls_no: The size of the PLL entries @plls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * Register the given set of PLLs with the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int s3c_plltab_register(struct cpufreq_frequency_table *plls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) unsigned int plls_no)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct cpufreq_frequency_table *vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) size = sizeof(*vals) * (plls_no + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) vals = kzalloc(size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (vals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) memcpy(vals, plls, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) pll_reg = vals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* write a terminating entry, we don't store it in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * table that is stored in the kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) vals += plls_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) vals->frequency = CPUFREQ_TABLE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) pr_info("%d PLL entries\n", plls_no);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) pr_err("no memory for PLL tables\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return vals ? 0 : -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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