^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * S3C2416/2450 CPUfreq Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011 Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * based on s3c64xx_cpufreq.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2009 Wolfson Microelectronics plc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static DEFINE_MUTEX(cpufreq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct s3c2416_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct clk *armdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct clk *armclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct clk *hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long regulator_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct regulator *vddarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct cpufreq_frequency_table *freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) bool is_dvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) bool disable_dvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct s3c2416_data s3c2416_cpufreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct s3c2416_dvfs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int vddarm_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int vddarm_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* pseudo-frequency for dvs mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FREQ_DVS 132333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* frequency to sleep and reboot in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * it's essential to leave dvs, as some boards do not reconfigure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * regulator on reboot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define FREQ_SLEEP 133333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Sources for the ARMCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SOURCE_HCLK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SOURCE_ARMDIV 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* S3C2416 only supports changing the voltage in the dvs-mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Voltages down to 1.0V seem to work, so we take what the regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * can get us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static struct s3c2416_dvfs s3c2416_dvfs_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) [SOURCE_HCLK] = { 950000, 1250000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [SOURCE_ARMDIV] = { 1250000, 1350000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct cpufreq_frequency_table s3c2416_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { 0, SOURCE_HCLK, FREQ_DVS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { 0, SOURCE_ARMDIV, 133333 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { 0, SOURCE_ARMDIV, 266666 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { 0, SOURCE_ARMDIV, 400000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { 0, 0, CPUFREQ_TABLE_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static struct cpufreq_frequency_table s3c2450_freq_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { 0, SOURCE_HCLK, FREQ_DVS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { 0, SOURCE_ARMDIV, 133500 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) { 0, SOURCE_ARMDIV, 267000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 0, SOURCE_ARMDIV, 534000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { 0, 0, CPUFREQ_TABLE_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static unsigned int s3c2416_cpufreq_get_speed(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (cpu != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* return our pseudo-frequency when in dvs mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (s3c_freq->is_dvs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return FREQ_DVS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return clk_get_rate(s3c_freq->armclk) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int s3c2416_cpufreq_set_armdiv(struct s3c2416_data *s3c_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (clk_get_rate(s3c_freq->armdiv) / 1000 != freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = clk_set_rate(s3c_freq->armdiv, freq * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pr_err("cpufreq: Failed to set armdiv rate %dkHz: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) freq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int s3c2416_cpufreq_enter_dvs(struct s3c2416_data *s3c_freq, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct s3c2416_dvfs *dvfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (s3c_freq->is_dvs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pr_debug("cpufreq: already in dvs mode, nothing to do\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pr_debug("cpufreq: switching armclk to hclk (%lukHz)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) clk_get_rate(s3c_freq->hclk) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ret = clk_set_parent(s3c_freq->armclk, s3c_freq->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pr_err("cpufreq: Failed to switch armclk to hclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* changing the core voltage is only allowed when in dvs mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (s3c_freq->vddarm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dvfs = &s3c2416_dvfs_table[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pr_debug("cpufreq: setting regulator to %d-%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dvfs->vddarm_min, dvfs->vddarm_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ret = regulator_set_voltage(s3c_freq->vddarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dvfs->vddarm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dvfs->vddarm_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* when lowering the voltage failed, there is nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pr_err("cpufreq: Failed to set VDDARM: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) s3c_freq->is_dvs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int s3c2416_cpufreq_leave_dvs(struct s3c2416_data *s3c_freq, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct s3c2416_dvfs *dvfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (!s3c_freq->is_dvs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pr_debug("cpufreq: not in dvs mode, so can't leave\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (s3c_freq->vddarm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dvfs = &s3c2416_dvfs_table[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pr_debug("cpufreq: setting regulator to %d-%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dvfs->vddarm_min, dvfs->vddarm_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = regulator_set_voltage(s3c_freq->vddarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dvfs->vddarm_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dvfs->vddarm_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pr_err("cpufreq: Failed to set VDDARM: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* force armdiv to hclk frequency for transition from dvs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (clk_get_rate(s3c_freq->armdiv) > clk_get_rate(s3c_freq->hclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pr_debug("cpufreq: force armdiv to hclk frequency (%lukHz)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) clk_get_rate(s3c_freq->hclk) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = s3c2416_cpufreq_set_armdiv(s3c_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) clk_get_rate(s3c_freq->hclk) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pr_err("cpufreq: Failed to set the armdiv to %lukHz: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) clk_get_rate(s3c_freq->hclk) / 1000, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) pr_debug("cpufreq: switching armclk parent to armdiv (%lukHz)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) clk_get_rate(s3c_freq->armdiv) / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ret = clk_set_parent(s3c_freq->armclk, s3c_freq->armdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pr_err("cpufreq: Failed to switch armclk clock parent to armdiv: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) s3c_freq->is_dvs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int s3c2416_cpufreq_set_target(struct cpufreq_policy *policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned int new_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int idx, ret, to_dvs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) mutex_lock(&cpufreq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) idx = s3c_freq->freq_table[index].driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (idx == SOURCE_HCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) to_dvs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* switching to dvs when it's not allowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (to_dvs && s3c_freq->disable_dvs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pr_debug("cpufreq: entering dvs mode not allowed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* When leavin dvs mode, always switch the armdiv to the hclk rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * The S3C2416 has stability issues when switching directly to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * higher frequencies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) new_freq = (s3c_freq->is_dvs && !to_dvs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ? clk_get_rate(s3c_freq->hclk) / 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) : s3c_freq->freq_table[index].frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (to_dvs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) pr_debug("cpufreq: enter dvs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret = s3c2416_cpufreq_enter_dvs(s3c_freq, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) } else if (s3c_freq->is_dvs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pr_debug("cpufreq: leave dvs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = s3c2416_cpufreq_leave_dvs(s3c_freq, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pr_debug("cpufreq: change armdiv to %dkHz\n", new_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = s3c2416_cpufreq_set_armdiv(s3c_freq, new_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) mutex_unlock(&cpufreq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void s3c2416_cpufreq_cfg_regulator(struct s3c2416_data *s3c_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int count, v, i, found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct cpufreq_frequency_table *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct s3c2416_dvfs *dvfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) count = regulator_count_voltages(s3c_freq->vddarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (count < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) pr_err("cpufreq: Unable to check supported voltages\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) cpufreq_for_each_valid_entry(pos, s3c_freq->freq_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dvfs = &s3c2416_dvfs_table[pos->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Check only the min-voltage, more is always ok on S3C2416 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) v = regulator_list_voltage(s3c_freq->vddarm, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (v >= dvfs->vddarm_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (!found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) pr_debug("cpufreq: %dkHz unsupported by regulator\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) pos->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pos->frequency = CPUFREQ_ENTRY_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* Guessed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) s3c_freq->regulator_latency = 1 * 1000 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int s3c2416_cpufreq_reboot_notifier_evt(struct notifier_block *this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned long event, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct cpufreq_policy *policy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mutex_lock(&cpufreq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* disable further changes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) s3c_freq->disable_dvs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) mutex_unlock(&cpufreq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* some boards don't reconfigure the regulator on reboot, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * could lead to undervolting the cpu when the clock is reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * Therefore we always leave the DVS mode on reboot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (s3c_freq->is_dvs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pr_debug("cpufreq: leave dvs on reboot\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) policy = cpufreq_cpu_get(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!policy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pr_debug("cpufreq: get no policy for cpu0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = cpufreq_driver_target(policy, FREQ_SLEEP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) cpufreq_cpu_put(policy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static struct notifier_block s3c2416_cpufreq_reboot_notifier = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .notifier_call = s3c2416_cpufreq_reboot_notifier_evt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int s3c2416_cpufreq_driver_init(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct cpufreq_frequency_table *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct clk *msysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (policy->cpu != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) msysclk = clk_get(NULL, "msysclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (IS_ERR(msysclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = PTR_ERR(msysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pr_err("cpufreq: Unable to obtain msysclk: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * S3C2416 and S3C2450 share the same processor-ID and also provide no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * other means to distinguish them other than through the rate of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * msysclk. On S3C2416 msysclk runs at 800MHz and on S3C2450 at 533MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) rate = clk_get_rate(msysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (rate == 800 * 1000 * 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pr_info("cpufreq: msysclk running at %lukHz, using S3C2416 frequency table\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) rate / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) s3c_freq->freq_table = s3c2416_freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) policy->cpuinfo.max_freq = 400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) } else if (rate / 1000 == 534000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pr_info("cpufreq: msysclk running at %lukHz, using S3C2450 frequency table\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) rate / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) s3c_freq->freq_table = s3c2450_freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) policy->cpuinfo.max_freq = 534000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* not needed anymore */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) clk_put(msysclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (s3c_freq->freq_table == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) pr_err("cpufreq: No frequency information for this CPU, msysclk at %lukHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) rate / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) s3c_freq->is_dvs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) s3c_freq->armdiv = clk_get(NULL, "armdiv");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (IS_ERR(s3c_freq->armdiv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = PTR_ERR(s3c_freq->armdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) pr_err("cpufreq: Unable to obtain ARMDIV: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) s3c_freq->hclk = clk_get(NULL, "hclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (IS_ERR(s3c_freq->hclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret = PTR_ERR(s3c_freq->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) pr_err("cpufreq: Unable to obtain HCLK: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) goto err_hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* chech hclk rate, we only support the common 133MHz for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * hclk could also run at 66MHz, but this not often used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) rate = clk_get_rate(s3c_freq->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (rate < 133 * 1000 * 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pr_err("cpufreq: HCLK not at 133MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) goto err_armclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) s3c_freq->armclk = clk_get(NULL, "armclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (IS_ERR(s3c_freq->armclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = PTR_ERR(s3c_freq->armclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pr_err("cpufreq: Unable to obtain ARMCLK: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) goto err_armclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) s3c_freq->vddarm = regulator_get(NULL, "vddarm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (IS_ERR(s3c_freq->vddarm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret = PTR_ERR(s3c_freq->vddarm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) goto err_vddarm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) s3c2416_cpufreq_cfg_regulator(s3c_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) s3c_freq->regulator_latency = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) cpufreq_for_each_entry(pos, s3c_freq->freq_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* special handling for dvs mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (pos->driver_data == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!s3c_freq->hclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pr_debug("cpufreq: %dkHz unsupported as it would need unavailable dvs mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pos->frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pos->frequency = CPUFREQ_ENTRY_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Check for frequencies we can generate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) rate = clk_round_rate(s3c_freq->armdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pos->frequency * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) rate /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (rate != pos->frequency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pr_debug("cpufreq: %dkHz unsupported by clock (clk_round_rate return %lu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pos->frequency, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pos->frequency = CPUFREQ_ENTRY_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Datasheet says PLL stabalisation time must be at least 300us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * so but add some fudge. (reference in LOCKCON0 register description)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) cpufreq_generic_init(policy, s3c_freq->freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) (500 * 1000) + s3c_freq->regulator_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) register_reboot_notifier(&s3c2416_cpufreq_reboot_notifier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) err_vddarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) clk_put(s3c_freq->armclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) err_armclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) clk_put(s3c_freq->hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) err_hclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) clk_put(s3c_freq->armdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static struct cpufreq_driver s3c2416_cpufreq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .verify = cpufreq_generic_frequency_table_verify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .target_index = s3c2416_cpufreq_set_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .get = s3c2416_cpufreq_get_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .init = s3c2416_cpufreq_driver_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .name = "s3c2416",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .attr = cpufreq_generic_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int __init s3c2416_cpufreq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return cpufreq_register_driver(&s3c2416_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) module_init(s3c2416_cpufreq_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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