Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *	http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * S3C2412 CPU Frequency scalling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/soc/samsung/s3c-cpufreq-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/soc/samsung/s3c-pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define S3C2412_CLKDIVN_PDIVN		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define S3C2412_CLKDIVN_HDIVN_MASK	(3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define S3C2412_CLKDIVN_ARMDIVN		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define S3C2412_CLKDIVN_DVSEN		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define S3C2412_CLKDIVN_HALFHCLK	(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define S3C2412_CLKDIVN_USB48DIV	(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define S3C2412_CLKDIVN_UARTDIV_MASK	(15<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define S3C2412_CLKDIVN_UARTDIV_SHIFT	(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define S3C2412_CLKDIVN_I2SDIV_MASK	(15<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define S3C2412_CLKDIVN_I2SDIV_SHIFT	(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define S3C2412_CLKDIVN_CAMDIV_MASK	(15<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define S3C2412_CLKDIVN_CAMDIV_SHIFT	(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* our clock resources. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static struct clk *xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static struct clk *fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static struct clk *hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static struct clk *armclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /* HDIV: 1, 2, 3, 4, 6, 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	unsigned int hdiv, pdiv, armdiv, dvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	unsigned long hclk, fclk, armclk, armdiv_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned long hclk_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	fclk = cfg->freq.fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	armclk = cfg->freq.armclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	hclk_max = cfg->max.hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/* We can't run hclk above armclk as at the best we have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 * have armclk and hclk in dvs mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (hclk_max > armclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		hclk_max = armclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		     __func__, fclk, armclk, hclk_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		     __func__, cfg->freq.fclk, cfg->freq.armclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		     cfg->freq.hclk, cfg->freq.pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	armdiv = fclk / armclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	if (armdiv < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		armdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	if (armdiv > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		armdiv = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	cfg->divs.arm_divisor = armdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	armdiv_clk = fclk / armdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	hdiv = armdiv_clk / hclk_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (hdiv < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		hdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	cfg->freq.hclk = hclk = armdiv_clk / hdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* set dvs depending on whether we reached armclk or not. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	cfg->divs.dvs = dvs = armclk < armdiv_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	/* update the actual armclk we achieved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	cfg->freq.armclk = dvs ? hclk : armdiv_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		     __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (hdiv > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		goto invalid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if ((hclk / pdiv) > cfg->max.pclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		pdiv++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	cfg->freq.pclk = hclk / pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (pdiv > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		goto invalid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	pdiv *= hdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* store the result, and then return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	cfg->divs.h_divisor = hdiv * armdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	cfg->divs.p_divisor = pdiv * armdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) invalid:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	unsigned long clkdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	unsigned long olddiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	olddiv = clkdiv = s3c24xx_read_clkdivn();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/* clear off current clock info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	clkdiv &= ~S3C2412_CLKDIVN_PDIVN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (cfg->divs.arm_divisor == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		clkdiv |= S3C2412_CLKDIVN_ARMDIVN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (cfg->divs.p_divisor != cfg->divs.h_divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		clkdiv |= S3C2412_CLKDIVN_PDIVN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	s3c24xx_write_clkdivn(clkdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* set the default cpu frequency information, based on an 200MHz part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  * as we have no other way of detecting the speed rating in software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.max		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		.fclk	= 200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		.hclk	= 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		.pclk	=  50000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.latency	= 5000000, /* 5ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.locktime_m	= 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.locktime_u	= 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.locktime_bits	= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.name		= "s3c2412",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.set_refresh	= s3c2412_cpufreq_setrefresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.set_divs	= s3c2412_cpufreq_setdivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.calc_divs	= s3c2412_cpufreq_calcdivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.calc_iotiming	= s3c2412_iotiming_calc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.set_iotiming	= s3c2412_iotiming_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.get_iotiming	= s3c2412_iotiming_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.debug_io_show  = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int s3c2412_cpufreq_add(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			       struct subsys_interface *sif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	unsigned long fclk_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	hclk = clk_get(NULL, "hclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (IS_ERR(hclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		pr_err("cannot find hclk clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	fclk = clk_get(NULL, "fclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (IS_ERR(fclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		pr_err("cannot find fclk clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		goto err_fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	fclk_rate = clk_get_rate(fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (fclk_rate > 200000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		pr_info("fclk %ld MHz, assuming 266MHz capable part\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			fclk_rate / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		s3c2412_cpufreq_info.max.fclk = 266000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		s3c2412_cpufreq_info.max.hclk = 133000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		s3c2412_cpufreq_info.max.pclk =  66000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	armclk = clk_get(NULL, "armclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (IS_ERR(armclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		pr_err("cannot find arm clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		goto err_armclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	xtal = clk_get(NULL, "xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	if (IS_ERR(xtal)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		pr_err("cannot find xtal clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		goto err_xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return s3c_cpufreq_register(&s3c2412_cpufreq_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) err_xtal:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	clk_put(armclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) err_armclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	clk_put(fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) err_fclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	clk_put(hclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct subsys_interface s3c2412_cpufreq_interface = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.name		= "s3c2412_cpufreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.subsys		= &s3c2412_subsys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.add_dev	= s3c2412_cpufreq_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int s3c2412_cpufreq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return subsys_interface_register(&s3c2412_cpufreq_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) arch_initcall(s3c2412_cpufreq_init);