^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2006-2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * S3C2410 CPU Frequency scaling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/soc/samsung/s3c-cpufreq-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/soc/samsung/s3c-pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S3C2410_CLKDIVN_PDIVN (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S3C2410_CLKDIVN_HDIVN (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 clkdiv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (cfg->divs.h_divisor == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) clkdiv |= S3C2410_CLKDIVN_HDIVN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (cfg->divs.p_divisor != cfg->divs.h_divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) clkdiv |= S3C2410_CLKDIVN_PDIVN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) s3c24xx_write_clkdivn(clkdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long hclk, fclk, pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int hdiv, pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned long hclk_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) fclk = cfg->freq.fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) hclk_max = cfg->max.hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) cfg->freq.armclk = fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) __func__, fclk, hclk_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) hdiv = (fclk > cfg->max.hclk) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) hclk = fclk / hdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (hclk > cfg->max.hclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) s3c_freq_dbg("%s: hclk too big\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) pclk = hclk / pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (pclk > cfg->max.pclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) s3c_freq_dbg("%s: pclk too big\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pdiv *= hdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* record the result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) cfg->divs.p_divisor = pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) cfg->divs.h_divisor = hdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .max = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .fclk = 200000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .hclk = 100000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .pclk = 50000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* transition latency is about 5ms worst-case, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * set 10ms to be sure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .latency = 10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .locktime_m = 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .locktime_u = 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .locktime_bits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .need_pll = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .name = "s3c2410",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .calc_iotiming = s3c2410_iotiming_calc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .set_iotiming = s3c2410_iotiming_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .get_iotiming = s3c2410_iotiming_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .set_fvco = s3c2410_set_fvco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .set_refresh = s3c2410_cpufreq_setrefresh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .set_divs = s3c2410_cpufreq_setdivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .calc_divs = s3c2410_cpufreq_calcdivs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int s3c2410_cpufreq_add(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct subsys_interface *sif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return s3c_cpufreq_register(&s3c2410_cpufreq_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct subsys_interface s3c2410_cpufreq_interface = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .name = "s3c2410_cpufreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .subsys = &s3c2410_subsys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .add_dev = s3c2410_cpufreq_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int __init s3c2410_cpufreq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return subsys_interface_register(&s3c2410_cpufreq_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) arch_initcall(s3c2410_cpufreq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int s3c2410a_cpufreq_add(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct subsys_interface *sif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* alter the maximum freq settings for S3C2410A. If a board knows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * it only has a maximum of 200, then it should register its own
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * limits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) s3c2410_cpufreq_info.max.fclk = 266000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) s3c2410_cpufreq_info.max.hclk = 133000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) s3c2410_cpufreq_info.max.pclk = 66500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) s3c2410_cpufreq_info.name = "s3c2410a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return s3c2410_cpufreq_add(dev, sif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct subsys_interface s3c2410a_cpufreq_interface = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .name = "s3c2410a_cpufreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .subsys = &s3c2410a_subsys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .add_dev = s3c2410a_cpufreq_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int __init s3c2410a_cpufreq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return subsys_interface_register(&s3c2410a_cpufreq_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) arch_initcall(s3c2410a_cpufreq_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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