^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef __ROCKCHIP_CPUFREQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define __ROCKCHIP_CPUFREQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #if IS_ENABLED(CONFIG_ARM_ROCKCHIP_CPUFREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) int rockchip_cpufreq_adjust_power_scale(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) int rockchip_cpufreq_opp_set_rate(struct device *dev, unsigned long target_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static inline int rockchip_cpufreq_adjust_power_scale(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static inline int rockchip_cpufreq_opp_set_rate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) unsigned long target_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #endif /* CONFIG_ARM_ROCKCHIP_CPUFREQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #endif