^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Rockchip CPUFreq Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/cpuidle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pm_opp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pm_qos.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/rockchip/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <soc/rockchip/rockchip_opp_select.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <soc/rockchip/rockchip_system_monitor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include "cpufreq-dt.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "rockchip-cpufreq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct cluster_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct list_head list_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct monitor_dev_info *mdev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct rockchip_opp_info opp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct freq_qos_request dsu_qos_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) cpumask_t cpus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int idle_threshold_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) bool is_idle_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) bool is_opp_shared_dsu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static LIST_HEAD(cluster_info_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int px30_get_soc_info(struct device *dev, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int *bin, int *process)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (!bin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (of_property_match_string(np, "nvmem-cell-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "performance") >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ret = rockchip_nvmem_cell_read_u8(np, "performance", &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dev_err(dev, "Failed to get soc performance value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *bin = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (*bin >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) dev_info(dev, "bin=%d\n", *bin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int rk3288_get_soc_info(struct device *dev, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int *bin, int *process)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (!bin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (of_property_match_string(np, "nvmem-cell-names", "special") >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = rockchip_nvmem_cell_read_u8(np, "special", &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dev_err(dev, "Failed to get soc special value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (value == 0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *bin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *bin = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (soc_is_rk3288w())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) name = "performance-w";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) name = "performance";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (of_property_match_string(np, "nvmem-cell-names", name) >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = rockchip_nvmem_cell_read_u8(np, name, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dev_err(dev, "Failed to get soc performance value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (value & 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *bin = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) else if (value & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *bin = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (*bin >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dev_info(dev, "bin=%d\n", *bin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!process)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (of_property_match_string(np, "nvmem-cell-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "process") >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret = rockchip_nvmem_cell_read_u8(np, "process", &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dev_err(dev, "Failed to get soc process version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (soc_is_rk3288() && (value == 0 || value == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *process = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (*process >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dev_info(dev, "process=%d\n", *process);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int rk3399_get_soc_info(struct device *dev, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int *bin, int *process)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (!bin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (of_property_match_string(np, "nvmem-cell-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "specification_serial_number") >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = rockchip_nvmem_cell_read_u8(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) "specification_serial_number",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "Failed to get specification_serial_number\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (value == 0xb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *bin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } else if (value == 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (of_property_match_string(np, "nvmem-cell-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "customer_demand") >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ret = rockchip_nvmem_cell_read_u8(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "customer_demand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_err(dev, "Failed to get customer_demand\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (value == 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *bin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *bin = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } else if (value == 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *bin = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (*bin >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dev_info(dev, "bin=%d\n", *bin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int rk3588_get_soc_info(struct device *dev, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int *bin, int *process)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u8 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (!bin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (of_property_match_string(np, "nvmem-cell-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "specification_serial_number") >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = rockchip_nvmem_cell_read_u8(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "specification_serial_number",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "Failed to get specification_serial_number\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* RK3588M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (value == 0xd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *bin = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (*bin < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) *bin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_info(dev, "bin=%d\n", *bin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int rk3588_change_length(struct device *dev, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int bin, int process, int volt_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned long old_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned int low_len_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 opp_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) clk = clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dev_warn(dev, "failed to get cpu clk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* RK3588 low speed grade should change to low length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (of_property_read_u32(np, "rockchip,pvtm-low-len-sel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) &low_len_sel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (volt_sel > low_len_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) opp_flag = OPP_LENGTH_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) old_rate = clk_get_rate(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = clk_set_rate(clk, old_rate | opp_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_err(dev, "failed to change length\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) clk_set_rate(clk, old_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int rk3588_set_supported_hw(struct device *dev, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int bin, int process, int volt_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct opp_table *opp_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 supported_hw[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (!of_property_read_bool(np, "rockchip,supported-hw"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* SoC Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) supported_hw[0] = BIT(bin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Speed Grade */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) supported_hw[1] = BIT(volt_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) opp_table = dev_pm_opp_set_supported_hw(dev, supported_hw, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (IS_ERR(opp_table)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(dev, "failed to set supported opp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return PTR_ERR(opp_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int rk3588_set_soc_info(struct device *dev, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int bin, int process, int volt_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (volt_sel < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (bin < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) bin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) rk3588_change_length(dev, np, bin, process, volt_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) rk3588_set_supported_hw(dev, np, bin, process, volt_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int rk3588_cpu_set_read_margin(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct rockchip_opp_info *opp_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 rm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (!opp_info->volt_rm_tbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (rm == opp_info->current_rm || rm == UINT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_dbg(dev, "set rm to %d\n", rm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (opp_info->grf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) regmap_write(opp_info->grf, 0x20, 0x001c0000 | (rm << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) regmap_write(opp_info->grf, 0x28, 0x003c0000 | (rm << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) regmap_write(opp_info->grf, 0x2c, 0x003c0000 | (rm << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) regmap_write(opp_info->grf, 0x30, 0x00200020);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) regmap_write(opp_info->grf, 0x30, 0x00200000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (opp_info->dsu_grf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) regmap_write(opp_info->dsu_grf, 0x20, 0x001c0000 | (rm << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) regmap_write(opp_info->dsu_grf, 0x28, 0x003c0000 | (rm << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) regmap_write(opp_info->dsu_grf, 0x2c, 0x003c0000 | (rm << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) regmap_write(opp_info->dsu_grf, 0x30, 0x001c0000 | (rm << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) regmap_write(opp_info->dsu_grf, 0x38, 0x001c0000 | (rm << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) regmap_write(opp_info->dsu_grf, 0x18, 0x40004000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) regmap_write(opp_info->dsu_grf, 0x18, 0x40000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) opp_info->current_rm = rm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int rv1126_get_soc_info(struct device *dev, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int *bin, int *process)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u8 value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (of_property_match_string(np, "nvmem-cell-names", "performance") >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = rockchip_nvmem_cell_read_u8(np, "performance", &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_err(dev, "Failed to get soc performance value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (value == 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *bin = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *bin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (*bin >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_info(dev, "bin=%d\n", *bin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const struct rockchip_opp_data px30_cpu_opp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .get_soc_info = px30_get_soc_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct rockchip_opp_data rk3288_cpu_opp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .get_soc_info = rk3288_get_soc_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const struct rockchip_opp_data rk3399_cpu_opp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .get_soc_info = rk3399_get_soc_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const struct rockchip_opp_data rk3588_cpu_opp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .get_soc_info = rk3588_get_soc_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .set_soc_info = rk3588_set_soc_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .set_read_margin = rk3588_cpu_set_read_margin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const struct rockchip_opp_data rv1126_cpu_opp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .get_soc_info = rv1126_get_soc_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct of_device_id rockchip_cpufreq_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .compatible = "rockchip,px30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .data = (void *)&px30_cpu_opp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .compatible = "rockchip,rk3288",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .data = (void *)&rk3288_cpu_opp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .compatible = "rockchip,rk3288w",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .data = (void *)&rk3288_cpu_opp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .compatible = "rockchip,rk3326",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .data = (void *)&px30_cpu_opp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .compatible = "rockchip,rk3399",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .data = (void *)&rk3399_cpu_opp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .compatible = "rockchip,rk3588",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .data = (void *)&rk3588_cpu_opp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .compatible = "rockchip,rv1109",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .data = (void *)&rv1126_cpu_opp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .compatible = "rockchip,rv1126",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .data = (void *)&rv1126_cpu_opp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static struct cluster_info *rockchip_cluster_info_lookup(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct cluster_info *cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) list_for_each_entry(cluster, &cluster_info_list, list_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (cpumask_test_cpu(cpu, &cluster->cpus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static int rockchip_cpufreq_set_volt(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct regulator *reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct dev_pm_opp_supply *supply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) char *reg_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_dbg(dev, "%s: %s voltages (uV): %lu %lu %lu\n", __func__, reg_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) supply->u_volt_min, supply->u_volt, supply->u_volt_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = regulator_set_voltage_triplet(reg, supply->u_volt_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) supply->u_volt, supply->u_volt_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_err(dev, "%s: failed to set voltage (%lu %lu %lu uV): %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) __func__, supply->u_volt_min, supply->u_volt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) supply->u_volt_max, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int cpu_opp_helper(struct dev_pm_set_opp_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct dev_pm_opp_supply *old_supply_vdd = &data->old_opp.supplies[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct dev_pm_opp_supply *old_supply_mem = &data->old_opp.supplies[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct dev_pm_opp_supply *new_supply_vdd = &data->new_opp.supplies[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct dev_pm_opp_supply *new_supply_mem = &data->new_opp.supplies[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct regulator *vdd_reg = data->regulators[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct regulator *mem_reg = data->regulators[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct device *dev = data->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct clk *clk = data->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct cluster_info *cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct rockchip_opp_info *opp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned long old_freq = data->old_opp.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned long new_freq = data->new_opp.rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u32 target_rm = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) cluster = rockchip_cluster_info_lookup(dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) opp_info = &cluster->opp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) rockchip_get_read_margin(dev, opp_info, new_supply_vdd->u_volt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) &target_rm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Change frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_dbg(dev, "%s: switching OPP: %lu Hz --> %lu Hz\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) old_freq, new_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Scaling up? Scale voltage before frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (new_freq >= old_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = rockchip_set_intermediate_rate(dev, opp_info, clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) old_freq, new_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev_err(dev, "%s: failed to set clk rate: %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) __func__, new_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ret = rockchip_cpufreq_set_volt(dev, mem_reg, new_supply_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) "mem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) goto restore_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = rockchip_cpufreq_set_volt(dev, vdd_reg, new_supply_vdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) "vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) goto restore_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) rockchip_set_read_margin(dev, opp_info, target_rm, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = clk_set_rate(clk, new_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev_err(dev, "%s: failed to set clk rate: %lu %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) __func__, new_freq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) goto restore_rm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Scaling down? Scale voltage after frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ret = rockchip_set_intermediate_rate(dev, opp_info, clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) old_freq, new_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) false, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev_err(dev, "%s: failed to set clk rate: %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) __func__, new_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) rockchip_set_read_margin(dev, opp_info, target_rm, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ret = clk_set_rate(clk, new_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dev_err(dev, "%s: failed to set clk rate: %lu %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) __func__, new_freq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) goto restore_rm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ret = rockchip_cpufreq_set_volt(dev, vdd_reg, new_supply_vdd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) "vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) goto restore_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ret = rockchip_cpufreq_set_volt(dev, mem_reg, new_supply_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "mem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) goto restore_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) restore_freq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (clk_set_rate(clk, old_freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev_err(dev, "%s: failed to restore old-freq (%lu Hz)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) __func__, old_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) restore_rm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) rockchip_get_read_margin(dev, opp_info, old_supply_vdd->u_volt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) &target_rm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) rockchip_set_read_margin(dev, opp_info, target_rm, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) restore_voltage:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) rockchip_cpufreq_set_volt(dev, mem_reg, old_supply_mem, "mem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) rockchip_cpufreq_set_volt(dev, vdd_reg, old_supply_vdd, "vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int rockchip_cpufreq_cluster_init(int cpu, struct cluster_info *cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct rockchip_opp_info *opp_info = &cluster->opp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct opp_table *pname_table = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct opp_table *reg_table = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct opp_table *opp_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) const char * const reg_names[] = {"cpu", "mem"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) char *reg_name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int bin = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int process = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int volt_sel = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dev = get_cpu_device(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) opp_info->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (of_find_property(dev->of_node, "cpu-supply", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) reg_name = "cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) else if (of_find_property(dev->of_node, "cpu0-supply", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) reg_name = "cpu0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) np = of_parse_phandle(dev->of_node, "operating-points-v2", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dev_warn(dev, "OPP-v2 not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) opp_info->grf = syscon_regmap_lookup_by_phandle(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) "rockchip,grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (IS_ERR(opp_info->grf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) opp_info->grf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ret = dev_pm_opp_of_get_sharing_cpus(dev, &cluster->cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_err(dev, "Failed to get sharing cpus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) goto np_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) cluster->is_opp_shared_dsu = of_property_read_bool(np, "rockchip,opp-shared-dsu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (!of_property_read_u32(np, "rockchip,idle-threshold-freq", &freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) cluster->idle_threshold_freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) rockchip_get_opp_data(rockchip_cpufreq_of_match, opp_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (opp_info->data && opp_info->data->set_read_margin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) opp_info->current_rm = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) opp_info->target_rm = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) opp_info->dsu_grf =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) syscon_regmap_lookup_by_phandle(np, "rockchip,dsu-grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (IS_ERR(opp_info->dsu_grf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) opp_info->dsu_grf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) rockchip_get_volt_rm_table(dev, np, "volt-mem-read-margin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) &opp_info->volt_rm_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) of_property_read_u32(np, "low-volt-mem-read-margin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) &opp_info->low_rm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (!of_property_read_u32(np, "intermediate-threshold-freq", &freq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) opp_info->intermediate_threshold_freq = freq * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) rockchip_init_read_margin(dev, opp_info, reg_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (opp_info->data && opp_info->data->get_soc_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) opp_info->data->get_soc_info(dev, np, &bin, &process);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) rockchip_get_scale_volt_sel(dev, "cpu_leakage", reg_name, bin, process,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) &cluster->scale, &volt_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (opp_info->data && opp_info->data->set_soc_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) opp_info->data->set_soc_info(dev, np, bin, process, volt_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) pname_table = rockchip_set_opp_prop_name(dev, process, volt_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (of_find_property(dev->of_node, "cpu-supply", NULL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) of_find_property(dev->of_node, "mem-supply", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) reg_table = dev_pm_opp_set_regulators(dev, reg_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ARRAY_SIZE(reg_names));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (IS_ERR(reg_table)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ret = PTR_ERR(reg_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) goto pname_opp_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) opp_table = dev_pm_opp_register_set_opp_helper(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) cpu_opp_helper);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (IS_ERR(opp_table)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ret = PTR_ERR(opp_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) goto reg_opp_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) reg_opp_table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (reg_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev_pm_opp_put_regulators(reg_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pname_opp_table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!IS_ERR_OR_NULL(pname_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) dev_pm_opp_put_prop_name(pname_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) np_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) int rockchip_cpufreq_adjust_power_scale(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct cluster_info *cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) cluster = rockchip_cluster_info_lookup(dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (!cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) rockchip_adjust_power_scale(dev, cluster->scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) rockchip_pvtpll_calibrate_opp(&cluster->opp_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) EXPORT_SYMBOL_GPL(rockchip_cpufreq_adjust_power_scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int rockchip_cpufreq_opp_set_rate(struct device *dev, unsigned long target_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct cluster_info *cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) cluster = rockchip_cluster_info_lookup(dev->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (!cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) rockchip_monitor_volt_adjust_lock(cluster->mdev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = dev_pm_opp_set_rate(dev, target_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) rockchip_monitor_volt_adjust_unlock(cluster->mdev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) EXPORT_SYMBOL_GPL(rockchip_cpufreq_opp_set_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static int rockchip_cpufreq_suspend(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret = cpufreq_generic_suspend(policy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) rockchip_monitor_suspend_low_temp_adjust(policy->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int rockchip_cpufreq_add_monitor(struct cluster_info *cluster,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct device *dev = cluster->opp_info.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct monitor_dev_profile *mdevp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct monitor_dev_info *mdev_info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) mdevp = kzalloc(sizeof(*mdevp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (!mdevp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) mdevp->type = MONITOR_TPYE_CPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) mdevp->low_temp_adjust = rockchip_monitor_cpu_low_temp_adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) mdevp->high_temp_adjust = rockchip_monitor_cpu_high_temp_adjust;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) mdevp->update_volt = rockchip_monitor_check_rate_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) mdevp->data = (void *)policy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) mdevp->opp_info = &cluster->opp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) cpumask_copy(&mdevp->allowed_cpus, policy->cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) mdev_info = rockchip_system_monitor_register(dev, mdevp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (IS_ERR(mdev_info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) kfree(mdevp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_err(dev, "failed to register system monitor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) mdev_info->devp = mdevp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) cluster->mdev_info = mdev_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int rockchip_cpufreq_remove_monitor(struct cluster_info *cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (cluster->mdev_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) kfree(cluster->mdev_info->devp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) rockchip_system_monitor_unregister(cluster->mdev_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) cluster->mdev_info = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static int rockchip_cpufreq_remove_dsu_qos(struct cluster_info *cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct cluster_info *ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (!cluster->is_opp_shared_dsu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) list_for_each_entry(ci, &cluster_info_list, list_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (ci->is_opp_shared_dsu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (freq_qos_request_active(&ci->dsu_qos_req))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) freq_qos_remove_request(&ci->dsu_qos_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static int rockchip_cpufreq_add_dsu_qos_req(struct cluster_info *cluster,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct device *dev = cluster->opp_info.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct cluster_info *ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (!cluster->is_opp_shared_dsu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) list_for_each_entry(ci, &cluster_info_list, list_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (ci->is_opp_shared_dsu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ret = freq_qos_add_request(&policy->constraints,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) &ci->dsu_qos_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) FREQ_QOS_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) FREQ_QOS_MIN_DEFAULT_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dev_err(dev, "failed to add dsu freq constraint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) rockchip_cpufreq_remove_dsu_qos(cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static int rockchip_cpufreq_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct cpufreq_policy *policy = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct cluster_info *cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) cluster = rockchip_cluster_info_lookup(policy->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (!cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (event == CPUFREQ_CREATE_POLICY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (rockchip_cpufreq_add_monitor(cluster, policy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (rockchip_cpufreq_add_dsu_qos_req(cluster, policy))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) } else if (event == CPUFREQ_REMOVE_POLICY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) rockchip_cpufreq_remove_monitor(cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) rockchip_cpufreq_remove_dsu_qos(cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static struct notifier_block rockchip_cpufreq_notifier_block = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .notifier_call = rockchip_cpufreq_notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static struct pm_qos_request idle_pm_qos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int idle_disable_refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static DEFINE_MUTEX(idle_disable_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int rockchip_cpufreq_idle_state_disable(struct cpumask *cpumask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int index, bool disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) mutex_lock(&idle_disable_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (disable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (idle_disable_refcnt == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) cpu_latency_qos_update_request(&idle_pm_qos, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) idle_disable_refcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (--idle_disable_refcnt == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) cpu_latency_qos_update_request(&idle_pm_qos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) PM_QOS_DEFAULT_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) mutex_unlock(&idle_disable_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static int rockchip_cpufreq_idle_state_disable(struct cpumask *cpumask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) int index, bool disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) for_each_cpu(cpu, cpumask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct cpuidle_device *dev = per_cpu(cpuidle_devices, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct cpuidle_driver *drv = cpuidle_get_cpu_driver(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (!dev || !drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (index >= drv->state_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) cpuidle_driver_state_disabled(drv, index, disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (disable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) for_each_cpu(cpu, cpumask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (cpu != smp_processor_id() && cpu_online(cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) wake_up_if_idle(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define cpu_to_dsu_freq(freq) ((freq) * 4 / 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static int rockchip_cpufreq_update_dsu_req(struct cluster_info *cluster,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) unsigned int freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct device *dev = cluster->opp_info.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) unsigned int dsu_freq = rounddown(cpu_to_dsu_freq(freq), 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (cluster->is_opp_shared_dsu ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) !freq_qos_request_active(&cluster->dsu_qos_req))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) dev_dbg(dev, "cpu to dsu: %u -> %u\n", freq, dsu_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return freq_qos_update_request(&cluster->dsu_qos_req, dsu_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static int rockchip_cpufreq_transition_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct cpufreq_freqs *freqs = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct cpufreq_policy *policy = freqs->policy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct cluster_info *cluster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) cluster = rockchip_cluster_info_lookup(policy->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (!cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return NOTIFY_BAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (event == CPUFREQ_PRECHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (cluster->idle_threshold_freq &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) freqs->new >= cluster->idle_threshold_freq &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) !cluster->is_idle_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) rockchip_cpufreq_idle_state_disable(policy->cpus, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) cluster->is_idle_disabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) } else if (event == CPUFREQ_POSTCHANGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (cluster->idle_threshold_freq &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) freqs->new < cluster->idle_threshold_freq &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) cluster->is_idle_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) rockchip_cpufreq_idle_state_disable(policy->cpus, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) cluster->is_idle_disabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) rockchip_cpufreq_update_dsu_req(cluster, freqs->new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static struct notifier_block rockchip_cpufreq_transition_notifier_block = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .notifier_call = rockchip_cpufreq_transition_notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int rockchip_cpufreq_panic_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) unsigned long v, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct cluster_info *ci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) list_for_each_entry(ci, &cluster_info_list, list_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) rockchip_opp_dump_cur_state(ci->opp_info.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static struct notifier_block rockchip_cpufreq_panic_notifier_block = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .notifier_call = rockchip_cpufreq_panic_notifier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static int __init rockchip_cpufreq_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct cluster_info *cluster, *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) struct cpufreq_dt_platform_data pdata = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) int cpu, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) cluster = rockchip_cluster_info_lookup(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (cluster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) cluster = kzalloc(sizeof(*cluster), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (!cluster) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) goto release_cluster_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ret = rockchip_cpufreq_cluster_init(cpu, cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) pr_err("Failed to initialize dvfs info cpu%d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) goto release_cluster_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) list_add(&cluster->list_head, &cluster_info_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) pdata.have_governor_per_policy = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) pdata.suspend = rockchip_cpufreq_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ret = cpufreq_register_notifier(&rockchip_cpufreq_notifier_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) CPUFREQ_POLICY_NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) pr_err("failed to register cpufreq notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) goto release_cluster_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (of_machine_is_compatible("rockchip,rk3588")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ret = cpufreq_register_notifier(&rockchip_cpufreq_transition_notifier_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) CPUFREQ_TRANSITION_NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) cpufreq_unregister_notifier(&rockchip_cpufreq_notifier_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) CPUFREQ_POLICY_NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) pr_err("failed to register cpufreq notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) goto release_cluster_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) cpu_latency_qos_add_request(&idle_pm_qos, PM_QOS_DEFAULT_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ret = atomic_notifier_chain_register(&panic_notifier_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) &rockchip_cpufreq_panic_notifier_block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) pr_err("failed to register cpufreq panic notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return PTR_ERR_OR_ZERO(platform_device_register_data(NULL, "cpufreq-dt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) -1, (void *)&pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) sizeof(struct cpufreq_dt_platform_data)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) release_cluster_info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) list_for_each_entry_safe(cluster, pos, &cluster_info_list, list_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) list_del(&cluster->list_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) kfree(cluster);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) module_init(rockchip_cpufreq_driver_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) MODULE_AUTHOR("Finley Xiao <finley.xiao@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) MODULE_DESCRIPTION("Rockchip cpufreq driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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