Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2008 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <mach/generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <mach/pxa3xx-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define HSS_104M	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define HSS_156M	(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define HSS_208M	(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define HSS_312M	(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SMCFS_78M	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SMCFS_104M	(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SMCFS_208M	(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SFLFS_104M	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SFLFS_156M	(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SFLFS_208M	(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SFLFS_312M	(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define XSPCLK_156M	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define XSPCLK_NONE	(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DMCFS_26M	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define DMCFS_260M	(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) struct pxa3xx_freq_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	unsigned int cpufreq_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	unsigned int core_xl : 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	unsigned int core_xn : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	unsigned int hss : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	unsigned int dmcfs : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	unsigned int smcfs : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	unsigned int sflfs : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	unsigned int df_clkdiv : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	int	vcc_core;	/* in mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int	vcc_sram;	/* in mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {									\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	.cpufreq_mhz	= cpufreq,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	.core_xl	= _xl,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.core_xn	= _xn,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.hss		= HSS_##_hss##M,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.dmcfs		= DMCFS_##_dmc##M,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.smcfs		= SMCFS_##_smc##M,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.sflfs		= SFLFS_##_sfl##M,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.df_clkdiv	= _dfi,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.vcc_core	= vcore,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.vcc_sram	= vsram,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static struct pxa3xx_freq_info pxa300_freqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	/*  CPU XL XN  HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	OP(104,  8, 1, 104, 260,  78, 104, 3, 1000, 1100), /* 104MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static struct pxa3xx_freq_info pxa320_freqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/*  CPU XL XN  HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	OP(104,  8, 1, 104, 260,  78, 104, 3, 1000, 1100), /* 104MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static unsigned int pxa3xx_freqs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static struct pxa3xx_freq_info *pxa3xx_freqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static struct cpufreq_frequency_table *pxa3xx_freqs_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int setup_freqs_table(struct cpufreq_policy *policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			     struct pxa3xx_freq_info *freqs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct cpufreq_frequency_table *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	table = kcalloc(num + 1, sizeof(*table), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	if (table == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	for (i = 0; i < num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		table[i].driver_data = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		table[i].frequency = freqs[i].cpufreq_mhz * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	table[num].driver_data = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	table[num].frequency = CPUFREQ_TABLE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	pxa3xx_freqs = freqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	pxa3xx_freqs_num = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	pxa3xx_freqs_table = table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	policy->freq_table = table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void __update_core_freq(struct pxa3xx_freq_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	uint32_t mask = ACCR_XN_MASK | ACCR_XL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	uint32_t accr = ACCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	uint32_t xclkcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	accr &= ~(ACCR_XN_MASK | ACCR_XL_MASK | ACCR_XSPCLK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	accr |= ACCR_XN(info->core_xn) | ACCR_XL(info->core_xl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/* No clock until core PLL is re-locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	accr |= ACCR_XSPCLK(XSPCLK_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	xclkcfg = (info->core_xn == 2) ? 0x3 : 0x2;	/* turbo bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	ACCR = accr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	__asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	while ((ACSR & mask) != (accr & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void __update_bus_freq(struct pxa3xx_freq_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	uint32_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	uint32_t accr = ACCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	mask = ACCR_SMCFS_MASK | ACCR_SFLFS_MASK | ACCR_HSS_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		ACCR_DMCFS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	accr &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	accr |= ACCR_SMCFS(info->smcfs) | ACCR_SFLFS(info->sflfs) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		ACCR_HSS(info->hss) | ACCR_DMCFS(info->dmcfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	ACCR = accr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	while ((ACSR & mask) != (accr & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static unsigned int pxa3xx_cpufreq_get(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return pxa3xx_get_clk_frequency_khz(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy, unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct pxa3xx_freq_info *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (policy->cpu != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	next = &pxa3xx_freqs[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	__update_core_freq(next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	__update_bus_freq(next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* set default policy and cpuinfo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	policy->min = policy->cpuinfo.min_freq = 104000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	policy->max = policy->cpuinfo.max_freq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		(cpu_is_pxa320()) ? 806000 : 624000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (cpu_is_pxa300() || cpu_is_pxa310())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		ret = setup_freqs_table(policy, pxa300_freqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 					ARRAY_SIZE(pxa300_freqs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (cpu_is_pxa320())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		ret = setup_freqs_table(policy, pxa320_freqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 					ARRAY_SIZE(pxa320_freqs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		pr_err("failed to setup frequency table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	pr_info("CPUFREQ support for PXA3xx initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static struct cpufreq_driver pxa3xx_cpufreq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.flags		= CPUFREQ_NEED_INITIAL_FREQ_CHECK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.verify		= cpufreq_generic_frequency_table_verify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.target_index	= pxa3xx_cpufreq_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.init		= pxa3xx_cpufreq_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.get		= pxa3xx_cpufreq_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.name		= "pxa3xx-cpufreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int __init cpufreq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (cpu_is_pxa3xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return cpufreq_register_driver(&pxa3xx_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) module_init(cpufreq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void __exit cpufreq_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	cpufreq_unregister_driver(&pxa3xx_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) module_exit(cpufreq_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MODULE_DESCRIPTION("CPU frequency scaling driver for PXA3xx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MODULE_LICENSE("GPL");