^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2002,2003 Intrinsyc Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * History:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 31-Jul-2002 : Initial version [FB]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 29-Jan-2003 : added PXA255 support [FB]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This driver may change the memory bus clock rate, but will not do any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * platform specific access timing changes... for example if you have flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * memory connected to CS0, you will need to register a platform specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * notifier which will adjust the memory access strobes to maintain a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * minimum strobe width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <mach/pxa2xx-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <mach/smemc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static unsigned int freq_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) module_param(freq_debug, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define freq_debug 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct regulator *vcc_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static unsigned int pxa27x_maxfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) module_param(pxa27x_maxfreq, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct pxa_cpufreq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct clk *clk_core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct pxa_cpufreq_data pxa_cpufreq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct pxa_freqs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int vmin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int vmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * PXA255 definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const struct pxa_freqs pxa255_run_freqs[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* CPU MEMBUS run turbo PXbus SDRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { 99500, -1, -1}, /* 99, 99, 50, 50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {132700, -1, -1}, /* 133, 133, 66, 66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {199100, -1, -1}, /* 199, 199, 99, 99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {265400, -1, -1}, /* 265, 265, 133, 66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {331800, -1, -1}, /* 331, 331, 166, 83 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {398100, -1, -1}, /* 398, 398, 196, 99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const struct pxa_freqs pxa255_turbo_freqs[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* CPU run turbo PXbus SDRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { 99500, -1, -1}, /* 99, 99, 50, 50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {199100, -1, -1}, /* 99, 199, 50, 99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {298500, -1, -1}, /* 99, 287, 50, 99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {298600, -1, -1}, /* 199, 287, 99, 99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {398100, -1, -1}, /* 199, 398, 99, 99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static struct cpufreq_frequency_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static struct cpufreq_frequency_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static unsigned int pxa255_turbo_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) module_param(pxa255_turbo_table, uint, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static struct pxa_freqs pxa27x_freqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {104000, 900000, 1705000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {156000, 1000000, 1705000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {208000, 1180000, 1705000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {312000, 1250000, 1705000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {416000, 1350000, 1705000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {520000, 1450000, 1705000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {624000, 1550000, 1705000 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct cpufreq_frequency_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pxa27x_freq_table[NUM_PXA27x_FREQS+1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) extern unsigned get_clk_frequency_khz(int info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #ifdef CONFIG_REGULATOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int vmin, vmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (!cpu_is_pxa27x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) vmin = pxa_freq->vmin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) vmax = pxa_freq->vmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if ((vmin == -1) || (vmax == -1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = regulator_set_voltage(vcc_core, vmin, vmax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pr_err("Failed to set vcc_core in [%dmV..%dmV]\n", vmin, vmax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void pxa_cpufreq_init_voltages(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) vcc_core = regulator_get(NULL, "vcc_core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (IS_ERR(vcc_core)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pr_info("Didn't find vcc_core regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) vcc_core = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pr_info("Found vcc_core regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int pxa_cpufreq_change_voltage(const struct pxa_freqs *pxa_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void pxa_cpufreq_init_voltages(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) const struct pxa_freqs **pxa_freqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (cpu_is_pxa25x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (!pxa255_turbo_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) *pxa_freqs = pxa255_run_freqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *freq_table = pxa255_run_freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *pxa_freqs = pxa255_turbo_freqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *freq_table = pxa255_turbo_freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } else if (cpu_is_pxa27x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) *pxa_freqs = pxa27x_freqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *freq_table = pxa27x_freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void pxa27x_guess_max_freq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!pxa27x_maxfreq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pxa27x_maxfreq = 416000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) pr_info("PXA CPU 27x max frequency not defined (pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pxa27x_maxfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pxa27x_maxfreq *= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static unsigned int pxa_cpufreq_get(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return (unsigned int) clk_get_rate(data->clk_core) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int pxa_set_target(struct cpufreq_policy *policy, unsigned int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct cpufreq_frequency_table *pxa_freqs_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) const struct pxa_freqs *pxa_freq_settings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct pxa_cpufreq_data *data = cpufreq_get_driver_data();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int new_freq_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Get the current policy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) new_freq_cpu = pxa_freq_settings[idx].khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (freq_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pr_debug("Changing CPU frequency from %d Mhz to %d Mhz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) policy->cur / 1000, new_freq_cpu / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (vcc_core && new_freq_cpu > policy->cur) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) clk_set_rate(data->clk_core, new_freq_cpu * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Even if voltage setting fails, we don't report it, as the frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * change succeeded. The voltage reduction is not a critical failure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * only power savings will suffer from this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Note: if the voltage change fails, and a return value is returned, a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * bug is triggered (seems a deadlock). Should anybody find out where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * the "return 0" should become a "return ret".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (vcc_core && new_freq_cpu < policy->cur)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int pxa_cpufreq_init(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct cpufreq_frequency_table *pxa255_freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) const struct pxa_freqs *pxa255_freqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* try to guess pxa27x cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (cpu_is_pxa27x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pxa27x_guess_max_freq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pxa_cpufreq_init_voltages();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* set default policy and cpuinfo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Generate pxa25x the run cpufreq_frequency_table struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pxa255_run_freq_table[i].driver_data = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Generate pxa25x the turbo cpufreq_frequency_table struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pxa255_turbo_freq_table[i].frequency =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pxa255_turbo_freqs[i].khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pxa255_turbo_freq_table[i].driver_data = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pxa255_turbo_table = !!pxa255_turbo_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Generate the pxa27x cpufreq_frequency_table struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) for (i = 0; i < NUM_PXA27x_FREQS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) freq = pxa27x_freqs[i].khz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (freq > pxa27x_maxfreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pxa27x_freq_table[i].frequency = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pxa27x_freq_table[i].driver_data = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pxa27x_freq_table[i].driver_data = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * Set the policy's minimum and maximum frequencies from the tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * just constructed. This sets cpuinfo.mxx_freq, min and max.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (cpu_is_pxa25x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pr_info("using %s frequency table\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pxa255_turbo_table ? "turbo" : "run");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) policy->freq_table = pxa255_freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) else if (cpu_is_pxa27x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) policy->freq_table = pxa27x_freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) pr_info("frequency change support initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static struct cpufreq_driver pxa_cpufreq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .verify = cpufreq_generic_frequency_table_verify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .target_index = pxa_set_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .init = pxa_cpufreq_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .get = pxa_cpufreq_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .name = "PXA2xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .driver_data = &pxa_cpufreq_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int __init pxa_cpu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pxa_cpufreq_data.clk_core = clk_get_sys(NULL, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (IS_ERR(pxa_cpufreq_data.clk_core))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return PTR_ERR(pxa_cpufreq_data.clk_core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (cpu_is_pxa25x() || cpu_is_pxa27x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = cpufreq_register_driver(&pxa_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static void __exit pxa_cpu_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) cpufreq_unregister_driver(&pxa_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) MODULE_AUTHOR("Intrinsyc Software Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) module_init(pxa_cpu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) module_exit(pxa_cpu_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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