^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * (c) 2003-2006 Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) struct powernow_k8_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) unsigned int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) u32 numps; /* number of p-states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) u32 batps; /* number of p-states supported on battery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* these values are constant when the PSB is used to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * vid/fid pairings, but are modified during the ->target() call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * when ACPI is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) u32 rvo; /* ramp voltage offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u32 irt; /* isochronous relief time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u32 vidmvs; /* usable value calculated from mvs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 vstable; /* voltage stabilization time, units 20 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 plllock; /* pll lock time, units 1 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 exttype; /* extended interface = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* keep track of the current fid / vid or pstate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 currvid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 currfid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* the powernow_table includes all frequency and vid/fid pairings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * fid are the lower 8 bits of the index, vid are the upper 8 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * frequency is in kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct cpufreq_frequency_table *powernow_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* the acpi table needs to be kept. it's only available if ACPI was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * used to determine valid frequency/vid/fid states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct acpi_processor_performance acpi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* we need to keep track of associated cores, but let cpufreq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * handle hotplug events - so just point at cpufreq pol->cpus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct cpumask *available_cores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* processor's cpuid instruction support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CPUID_PROCESSOR_SIGNATURE 1 /* function 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CPUID_XFAM 0x0ff00000 /* extended family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CPUID_XFAM_K8 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CPUID_XMOD 0x000f0000 /* extended model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CPUID_XMOD_REV_MASK 0x000c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CPUID_XFAM_10H 0x00100000 /* family 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CPUID_USE_XFAM_XMOD 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CPUID_GET_MAX_CAPABILITIES 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CPUID_FREQ_VOLT_CAPABILITIES 0x80000007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define P_STATE_TRANSITION_CAPABLE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* the register number is placed in ecx, and the data is returned in edx:eax. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MSR_FIDVID_CTL 0xc0010041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MSR_FIDVID_STATUS 0xc0010042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Field definitions within the FID VID Low Control MSR : */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MSR_C_LO_INIT_FID_VID 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MSR_C_LO_NEW_VID 0x00003f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MSR_C_LO_NEW_FID 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MSR_C_LO_VID_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Field definitions within the FID VID High Control MSR : */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MSR_C_HI_STP_GNT_TO 0x000fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Field definitions within the FID VID Low Status MSR : */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MSR_S_LO_CHANGE_PENDING 0x80000000 /* cleared when completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MSR_S_LO_MAX_RAMP_VID 0x3f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MSR_S_LO_MAX_FID 0x003f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MSR_S_LO_START_FID 0x00003f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MSR_S_LO_CURRENT_FID 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Field definitions within the FID VID High Status MSR : */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MSR_S_HI_MIN_WORKING_VID 0x3f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MSR_S_HI_MAX_WORKING_VID 0x003f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MSR_S_HI_START_VID 0x00003f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MSR_S_HI_CURRENT_VID 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MSR_C_HI_STP_GNT_BENIGN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * There are restrictions frequencies have to follow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * - only 1 entry in the low fid table ( <=1.4GHz )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * - lowest entry in the high fid table must be >= 2 * the entry in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * low fid table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * - lowest entry in the high fid table must be a <= 200MHz + 2 * the entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * in the low fid table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * - the parts can only step at <= 200 MHz intervals, odd fid values are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * supported in revision G and later revisions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * - lowest frequency must be >= interprocessor hypertransport link speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * (only applies to MP systems obviously)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* fids (frequency identifiers) are arranged in 2 tables - lo and hi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define LO_FID_TABLE_TOP 7 /* fid values marking the boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HI_FID_TABLE_BOTTOM 8 /* between the low and high tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LO_VCOFREQ_TABLE_TOP 1400 /* corresponding vco frequency values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HI_VCOFREQ_TABLE_BOTTOM 1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MIN_FREQ_RESOLUTION 200 /* fids jump by 2 matching freq jumps by 200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MAX_FID 0x2a /* Spec only gives FID values as far as 5 GHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define LEAST_VID 0x3e /* Lowest (numerically highest) useful vid value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MIN_FREQ 800 /* Min and max freqs, per spec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MAX_FREQ 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define INVALID_FID_MASK 0xffffffc0 /* not a valid fid if these bits are set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define INVALID_VID_MASK 0xffffffc0 /* not a valid vid if these bits are set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define VID_OFF 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define STOP_GRANT_5NS 1 /* min poss memory access latency for voltage change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PLL_LOCK_CONVERSION (1000/5) /* ms to ns, then divide by clock period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MAXIMUM_VID_STEPS 1 /* Current cpus only allow a single step of 25mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define VST_UNITS_20US 20 /* Voltage Stabilization Time is in units of 20us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Most values of interest are encoded in a single field of the _PSS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * entries: the "control" value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IRT_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RVO_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define EXT_TYPE_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PLL_L_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MVS_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define VST_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define VID_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IRT_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RVO_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define EXT_TYPE_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PLL_L_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MVS_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define VST_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define VID_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define FID_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define EXT_VID_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define EXT_FID_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Version 1.4 of the PSB table. This table is constructed by BIOS and is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * to tell the OS's power management driver which VIDs and FIDs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * supported by this particular processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * If the data in the PSB / PST is wrong, then this driver will program the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * wrong values into hardware, which is very likely to lead to a crash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PSB_ID_STRING "AMDK7PNOW!"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PSB_ID_STRING_LEN 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PSB_VERSION_1_4 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct psb_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u8 signature[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u8 tableversion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u8 flags1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u16 vstable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 flags2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u8 num_tables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 cpuid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 plllocktime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 maxfid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 maxvid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u8 numps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Pairs of fid/vid values are appended to the version 1.4 PSB table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct pst_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u8 fid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int core_voltage_pre_transition(struct powernow_k8_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 reqvid, u32 regfid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int core_voltage_post_transition(struct powernow_k8_data *data, u32 reqvid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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