^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * that is iMac G5 and latest single CPU desktop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/sections.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/smu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/pmac_pfunc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DBG(fmt...) pr_debug(fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* see 970FX user manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SCOM_PCR 0x0aa001 /* PCR scom addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCR_SPEED_MASK 0x000e0000U /* speed mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCR_SPEED_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCR_TARGET_TIME_MASK 0x00006000U /* target time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SCOM_PSR 0x408001 /* PSR scom addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* warning: PSR is a 64 bits register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PSR_CUR_SPEED_SHIFT (56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * The G5 only supports two frequencies (Quarter speed is not supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CPUFREQ_HIGH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CPUFREQ_LOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static struct cpufreq_frequency_table g5_cpu_freqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {0, CPUFREQ_HIGH, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {0, CPUFREQ_LOW, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {0, 0, CPUFREQ_TABLE_END},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Power mode data is an array of the 32 bits PCR values to use for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * the various frequencies, retrieved from the device-tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int g5_pmode_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static void (*g5_switch_volt)(int speed_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int (*g5_switch_freq)(int speed_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static int (*g5_query_freq)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static unsigned long transition_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #ifdef CONFIG_PMAC_SMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const u32 *g5_pmode_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int g5_pmode_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static struct smu_sdbp_fvt *g5_fvt_table; /* table of op. points */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int g5_fvt_count; /* number of op. points */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int g5_fvt_cur; /* current op. point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * SMU based voltage switching for Neo2 platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void g5_smu_switch_volt(int speed_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct smu_simple_cmd cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) DECLARE_COMPLETION_ONSTACK(comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) &comp, 'V', 'S', 'L', 'E', 'W',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 0xff, g5_fvt_cur+1, speed_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) wait_for_completion(&comp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Platform function based voltage/vdnap switching for Neo2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static struct pmf_function *pfunc_set_vdnap0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static struct pmf_function *pfunc_vdnap0_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void g5_vdnap_switch_volt(int speed_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct pmf_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 slew, done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) args.count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) args.u[0].p = &slew;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pmf_call_one(pfunc_set_vdnap0, &args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* It's an irq GPIO so we should be able to just block here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * I'll do that later after I've properly tested the IRQ code for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * platform functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) timeout = jiffies + HZ/10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) while(!time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) args.count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) args.u[0].p = &done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pmf_call_one(pfunc_vdnap0_complete, &args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) usleep_range(1000, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (done == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pr_warn("Timeout in clock slewing !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * SCOM based frequency switching for 970FX rev3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int g5_scom_switch_freq(int speed_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* If frequency is going up, first ramp up the voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (speed_mode < g5_pmode_cur)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) g5_switch_volt(speed_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Clear PCR high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) scom970_write(SCOM_PCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Clear PCR low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Set PCR low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) scom970_write(SCOM_PCR, PCR_HILO_SELECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) g5_pmode_data[speed_mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Wait for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) for (to = 0; to < 10; to++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long psr = scom970_read(SCOM_PSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if ((psr & PSR_CMD_RECEIVED) == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) (((psr >> PSR_CUR_SPEED_SHIFT) ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (psr & PSR_CMD_COMPLETED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* If frequency is going down, last ramp the voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (speed_mode > g5_pmode_cur)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) g5_switch_volt(speed_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) g5_pmode_cur = speed_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int g5_scom_query_freq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned long psr = scom970_read(SCOM_PSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) for (i = 0; i <= g5_pmode_max; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Fake voltage switching for platforms with missing support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void g5_dummy_switch_volt(int speed_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #endif /* CONFIG_PMAC_SMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * Platform function based voltage switching for PowerMac7,2 & 7,3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static struct pmf_function *pfunc_cpu0_volt_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static struct pmf_function *pfunc_cpu0_volt_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static struct pmf_function *pfunc_cpu1_volt_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct pmf_function *pfunc_cpu1_volt_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void g5_pfunc_switch_volt(int speed_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (speed_mode == CPUFREQ_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (pfunc_cpu0_volt_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pmf_call_one(pfunc_cpu0_volt_high, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (pfunc_cpu1_volt_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pmf_call_one(pfunc_cpu1_volt_high, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (pfunc_cpu0_volt_low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pmf_call_one(pfunc_cpu0_volt_low, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (pfunc_cpu1_volt_low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pmf_call_one(pfunc_cpu1_volt_low, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) usleep_range(10000, 10000); /* should be faster , to fix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Platform function based frequency switching for PowerMac7,2 & 7,3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static struct pmf_function *pfunc_cpu_setfreq_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static struct pmf_function *pfunc_cpu_setfreq_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct pmf_function *pfunc_cpu_getfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct pmf_function *pfunc_slewing_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int g5_pfunc_switch_freq(int speed_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct pmf_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) DBG("g5_pfunc_switch_freq(%d)\n", speed_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* If frequency is going up, first ramp up the voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (speed_mode < g5_pmode_cur)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) g5_switch_volt(speed_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Do it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (speed_mode == CPUFREQ_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pr_warn("pfunc switch error %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* It's an irq GPIO so we should be able to just block here,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * I'll do that later after I've properly tested the IRQ code for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * platform functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) timeout = jiffies + HZ/10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) while(!time_after(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) args.count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) args.u[0].p = &done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pmf_call_one(pfunc_slewing_done, &args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) usleep_range(500, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (done == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pr_warn("Timeout in clock slewing !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* If frequency is going down, last ramp the voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (speed_mode > g5_pmode_cur)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) g5_switch_volt(speed_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) g5_pmode_cur = speed_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int g5_pfunc_query_freq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct pmf_args args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) args.count = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) args.u[0].p = &val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pmf_call_one(pfunc_cpu_getfreq, &args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return val ? CPUFREQ_HIGH : CPUFREQ_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Common interface to the cpufreq core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int g5_cpufreq_target(struct cpufreq_policy *policy, unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return g5_switch_freq(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return g5_cpu_freqs[g5_pmode_cur].frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) cpufreq_generic_init(policy, g5_cpu_freqs, transition_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static struct cpufreq_driver g5_cpufreq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .name = "powermac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .flags = CPUFREQ_CONST_LOOPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .init = g5_cpufreq_cpu_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .verify = cpufreq_generic_frequency_table_verify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .target_index = g5_cpufreq_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .get = g5_cpufreq_get_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .attr = cpufreq_generic_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #ifdef CONFIG_PMAC_SMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int __init g5_neo2_cpufreq_init(struct device_node *cpunode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned int psize, ssize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned long max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) char *freq_method, *volt_method;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) const u32 *valp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 pvr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int use_volts_vdnap = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int use_volts_smu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Check supported platforms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (of_machine_is_compatible("PowerMac8,1") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) of_machine_is_compatible("PowerMac8,2") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) of_machine_is_compatible("PowerMac9,1") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) of_machine_is_compatible("PowerMac12,1"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) use_volts_smu = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) else if (of_machine_is_compatible("PowerMac11,2"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) use_volts_vdnap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Check 970FX for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) valp = of_get_property(cpunode, "cpu-version", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!valp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DBG("No cpu-version property !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) goto bail_noprops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pvr_hi = (*valp) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (pvr_hi != 0x3c && pvr_hi != 0x44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pr_err("Unsupported CPU version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) goto bail_noprops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Look for the powertune data in the device-tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (!g5_pmode_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DBG("No power-mode-data !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) goto bail_noprops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) g5_pmode_max = psize / sizeof(u32) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (use_volts_smu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) const struct smu_sdbp_header *shdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Look for the FVT table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!shdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) goto bail_noprops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ssize = (shdr->len * sizeof(u32)) - sizeof(*shdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) g5_fvt_count = ssize / sizeof(*g5_fvt_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) g5_fvt_cur = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Sanity checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (g5_fvt_count < 1 || g5_pmode_max < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) goto bail_noprops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) g5_switch_volt = g5_smu_switch_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) volt_method = "SMU";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) } else if (use_volts_vdnap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct device_node *root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) root = of_find_node_by_path("/");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (root == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pr_err("Can't find root of device tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) goto bail_noprops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pfunc_vdnap0_complete =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) pmf_find_function(root, "slewing-done");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) of_node_put(root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (pfunc_set_vdnap0 == NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pfunc_vdnap0_complete == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) pr_err("Can't find required platform function\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) goto bail_noprops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) g5_switch_volt = g5_vdnap_switch_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) volt_method = "GPIO";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) g5_switch_volt = g5_dummy_switch_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) volt_method = "none";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * From what I see, clock-frequency is always the maximal frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * The current driver can not slew sysclk yet, so we really only deal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * with powertune steps for now. We also only implement full freq and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * half freq in this version. So far, I haven't yet seen a machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * supporting anything else.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) valp = of_get_property(cpunode, "clock-frequency", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!valp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) max_freq = (*valp)/1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) g5_cpu_freqs[0].frequency = max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) g5_cpu_freqs[1].frequency = max_freq/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Set callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) transition_latency = 12000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) g5_switch_freq = g5_scom_switch_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) g5_query_freq = g5_scom_query_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) freq_method = "SCOM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Force apply current frequency to make sure everything is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * sync (voltage is right for example). Firmware may leave us with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * a strange setting ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) g5_switch_volt(CPUFREQ_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) g5_pmode_cur = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) g5_switch_freq(g5_query_freq());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pr_info("Registering G5 CPU frequency driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pr_info("Frequency method: %s, Voltage method: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) freq_method, volt_method);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) g5_cpu_freqs[1].frequency/1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) g5_cpu_freqs[0].frequency/1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) g5_cpu_freqs[g5_pmode_cur].frequency/1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) rc = cpufreq_register_driver(&g5_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* We keep the CPU node on hold... hopefully, Apple G5 don't have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * hotplug CPU with a dynamic device-tree ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) bail_noprops:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) of_node_put(cpunode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #endif /* CONFIG_PMAC_SMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int __init g5_pm72_cpufreq_init(struct device_node *cpunode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct device_node *cpuid = NULL, *hwclock = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) const u8 *eeprom = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) const u32 *valp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u64 max_freq, min_freq, ih, il;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int has_volt = 1, rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) " RackMac3,1...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Lookup the cpuid eeprom node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (cpuid != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) eeprom = of_get_property(cpuid, "cpuid", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (eeprom == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pr_err("Can't find cpuid EEPROM !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Lookup the i2c hwclock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) for_each_node_by_name(hwclock, "i2c-hwclock") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) const char *loc = of_get_property(hwclock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) "hwctrl-location", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (loc == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (strcmp(loc, "CPU CLOCK"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!of_get_property(hwclock, "platform-get-frequency", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (hwclock == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) pr_err("Can't find i2c clock chip !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) DBG("cpufreq: i2c clock chip found: %pOF\n", hwclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* Now get all the platform functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pfunc_cpu_getfreq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) pmf_find_function(hwclock, "get-frequency");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pfunc_cpu_setfreq_high =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) pmf_find_function(hwclock, "set-frequency-high");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pfunc_cpu_setfreq_low =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) pmf_find_function(hwclock, "set-frequency-low");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) pfunc_slewing_done =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) pmf_find_function(hwclock, "slewing-done");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) pfunc_cpu0_volt_high =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pmf_find_function(hwclock, "set-voltage-high-0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pfunc_cpu0_volt_low =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pmf_find_function(hwclock, "set-voltage-low-0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) pfunc_cpu1_volt_high =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) pmf_find_function(hwclock, "set-voltage-high-1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) pfunc_cpu1_volt_low =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) pmf_find_function(hwclock, "set-voltage-low-1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Check we have minimum requirements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pr_err("Can't find platform functions !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Check that we have complete sets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) pmf_put_function(pfunc_cpu0_volt_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) pmf_put_function(pfunc_cpu0_volt_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) has_volt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (!has_volt ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) pmf_put_function(pfunc_cpu1_volt_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pmf_put_function(pfunc_cpu1_volt_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Note: The device tree also contains a "platform-set-values"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * function for which I haven't quite figured out the usage. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * might have to be called on init and/or wakeup, I'm not too sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * but things seem to work fine without it so far ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* Get max frequency from device-tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) valp = of_get_property(cpunode, "clock-frequency", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (!valp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) pr_err("Can't find CPU frequency !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) max_freq = (*valp)/1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Now calculate reduced frequency by using the cpuid input freq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * ratio. This requires 64 bits math unless we are willing to lose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * some precision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ih = *((u32 *)(eeprom + 0x10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) il = *((u32 *)(eeprom + 0x20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Check for machines with no useful settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (il == ih) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pr_warn("No low frequency mode available on this model !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) min_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (ih != 0 && il != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) min_freq = (max_freq * il) / ih;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (min_freq >= max_freq || min_freq < 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) pr_err("Can't calculate low frequency !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) rc = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) g5_cpu_freqs[0].frequency = max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) g5_cpu_freqs[1].frequency = min_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Based on a measurement on Xserve G5, rounded up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) transition_latency = 10 * NSEC_PER_MSEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Set callbacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) g5_switch_volt = g5_pfunc_switch_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) g5_switch_freq = g5_pfunc_switch_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) g5_query_freq = g5_pfunc_query_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* Force apply current frequency to make sure everything is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * sync (voltage is right for example). Firmware may leave us with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * a strange setting ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) g5_switch_volt(CPUFREQ_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) g5_pmode_cur = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) g5_switch_freq(g5_query_freq());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) pr_info("Registering G5 CPU frequency driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) pr_info("Frequency method: i2c/pfunc, Voltage method: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) has_volt ? "i2c/pfunc" : "none");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) g5_cpu_freqs[1].frequency/1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) g5_cpu_freqs[0].frequency/1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) g5_cpu_freqs[g5_pmode_cur].frequency/1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) rc = cpufreq_register_driver(&g5_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) bail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (rc != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) pmf_put_function(pfunc_cpu_getfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) pmf_put_function(pfunc_cpu_setfreq_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) pmf_put_function(pfunc_cpu_setfreq_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pmf_put_function(pfunc_slewing_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) pmf_put_function(pfunc_cpu0_volt_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) pmf_put_function(pfunc_cpu0_volt_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pmf_put_function(pfunc_cpu1_volt_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) pmf_put_function(pfunc_cpu1_volt_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) of_node_put(hwclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) of_node_put(cpuid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) of_node_put(cpunode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int __init g5_cpufreq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct device_node *cpunode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Get first CPU node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) cpunode = of_cpu_device_node_get(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) if (cpunode == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) pr_err("Can't find any CPU node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (of_machine_is_compatible("PowerMac7,2") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) of_machine_is_compatible("PowerMac7,3") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) of_machine_is_compatible("RackMac3,1"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) rc = g5_pm72_cpufreq_init(cpunode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #ifdef CONFIG_PMAC_SMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) rc = g5_neo2_cpufreq_init(cpunode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #endif /* CONFIG_PMAC_SMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) module_init(g5_cpufreq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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