^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2004 John Steele Scott <toojays@toojays.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * TODO: Need a big cleanup here. Basically, we need to have different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * cpufreq_driver structures for the different type of HW instead of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * current mess. We also need to better deal with the detection of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * type of machine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/adb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/hardirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/pmac_feature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/sections.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/mpic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/keylargo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/switch_to.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* WARNING !!! This will cause calibrate_delay() to be called,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * but this is an __init function ! So you MUST go edit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * init/main.c to make it non-init before enabling DEBUG_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #undef DEBUG_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) extern void low_choose_7447a_dfs(int dfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) extern void low_choose_750fx_pll(int pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) extern void low_sleep_handler(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Currently, PowerMac cpufreq supports only high & low frequencies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * that are set by the firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static unsigned int low_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static unsigned int hi_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static unsigned int cur_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static unsigned int sleep_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static unsigned long transition_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Different models uses different mechanisms to switch the frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int (*set_speed_proc)(int low_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static unsigned int (*get_speed_proc)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Some definitions used by the various speedprocs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static u32 voltage_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static u32 frequency_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static u32 slew_done_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int no_schedule;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int has_cpu_l2lve;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int is_pmu_based;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* There are only two frequency states for each processor. Values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * are in kHz for the time being.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CPUFREQ_HIGH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CPUFREQ_LOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static struct cpufreq_frequency_table pmac_cpu_freqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {0, CPUFREQ_HIGH, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {0, CPUFREQ_LOW, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {0, 0, CPUFREQ_TABLE_END},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static inline void local_delay(unsigned long ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (no_schedule)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mdelay(ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) msleep(ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #ifdef DEBUG_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static inline void debug_calc_bogomips(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* This will cause a recalc of bogomips and display the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * result. We backup/restore the value to avoid affecting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * core cpufreq framework's own calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned long save_lpj = loops_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) calibrate_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) loops_per_jiffy = save_lpj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif /* DEBUG_FREQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Switch CPU speed under 750FX CPU control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int cpu_750fx_cpu_speed(int low_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 hid2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (low_speed == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* ramping up, set voltage first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Make sure we sleep for at least 1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) local_delay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* tweak L2 for high voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (has_cpu_l2lve) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) hid2 = mfspr(SPRN_HID2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) hid2 &= ~0x2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mtspr(SPRN_HID2, hid2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #ifdef CONFIG_PPC_BOOK3S_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) low_choose_750fx_pll(low_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (low_speed == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* tweak L2 for low voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (has_cpu_l2lve) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) hid2 = mfspr(SPRN_HID2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) hid2 |= 0x2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mtspr(SPRN_HID2, hid2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* ramping down, set voltage last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) local_delay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static unsigned int cpu_750fx_get_cpu_speed(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (mfspr(SPRN_HID1) & HID1_PS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return low_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return hi_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Switch CPU speed using DFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int dfs_set_cpu_speed(int low_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (low_speed == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* ramping up, set voltage first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Make sure we sleep for at least 1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) local_delay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* set frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #ifdef CONFIG_PPC_BOOK3S_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) low_choose_7447a_dfs(low_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (low_speed == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* ramping down, set voltage last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) local_delay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static unsigned int dfs_get_cpu_speed(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (mfspr(SPRN_HID1) & HID1_DFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return low_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return hi_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Switch CPU speed using slewing GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int gpios_set_cpu_speed(int low_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int gpio, timeout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* If ramping up, set voltage first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (low_speed == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Delay is way too big but it's ok, we schedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) local_delay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Set frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (low_speed == ((gpio & 0x01) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) goto skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, frequency_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) low_speed ? 0x04 : 0x05);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (++timeout > 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) local_delay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, slew_done_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } while((gpio & 0x02) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) skip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* If ramping down, set voltage last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (low_speed == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Delay is way too big but it's ok, we schedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) local_delay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #ifdef DEBUG_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) debug_calc_bogomips();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Switch CPU speed under PMU control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int pmu_set_cpu_speed(int low_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct adb_request req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long save_l2cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned long save_l3cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned int pic_prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #ifdef DEBUG_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) pmu_suspend();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Disable all interrupt sources on openpic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pic_prio = mpic_cpu_get_priority();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) mpic_cpu_set_priority(0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Make sure the decrementer won't interrupt us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) asm volatile("mtdec %0" : : "r" (0x7fffffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Make sure any pending DEC interrupt occurring while we did
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * the above didn't re-enable the DEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) asm volatile("mtdec %0" : : "r" (0x7fffffff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* We can now disable MSR_EE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Giveup the FPU & vec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) enable_kernel_fp();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #ifdef CONFIG_ALTIVEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (cpu_has_feature(CPU_FTR_ALTIVEC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) enable_kernel_altivec();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #endif /* CONFIG_ALTIVEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Save & disable L2 and L3 caches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) save_l3cr = _get_L3CR(); /* (returns -1 if not available) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) save_l2cr = _get_L2CR(); /* (returns -1 if not available) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Send the new speed command. My assumption is that this command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * will cause PLL_CFG[0..3] to be changed next time CPU goes to sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pmu_request(&req, NULL, 6, PMU_CPU_SPEED, 'W', 'O', 'O', 'F', low_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) while (!req.complete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pmu_poll();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Prepare the northbridge for the speed transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* Call low level code to backup CPU state and recover from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * hardware reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) low_sleep_handler();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Restore the northbridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Restore L2 cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (save_l2cr != 0xffffffff && (save_l2cr & L2CR_L2E) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) _set_L2CR(save_l2cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Restore L3 cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (save_l3cr != 0xffffffff && (save_l3cr & L3CR_L3E) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) _set_L3CR(save_l3cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Restore userland MMU context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) switch_mmu_context(NULL, current->active_mm, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #ifdef DEBUG_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Restore low level PMU operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) pmu_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Restore decrementer; we'll take a decrementer interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * as soon as interrupts are re-enabled and the generic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * clockevents code will reprogram it with the right value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) set_dec(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Restore interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mpic_cpu_set_priority(pic_prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Let interrupts flow again ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #ifdef DEBUG_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) debug_calc_bogomips();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) pmu_resume();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int do_set_cpu_speed(struct cpufreq_policy *policy, int speed_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned long l3cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static unsigned long prev_l3cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (speed_mode == CPUFREQ_LOW &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) cpu_has_feature(CPU_FTR_L3CR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) l3cr = _get_L3CR();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (l3cr & L3CR_L3E) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) prev_l3cr = l3cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) _set_L3CR(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) set_speed_proc(speed_mode == CPUFREQ_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (speed_mode == CPUFREQ_HIGH &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) cpu_has_feature(CPU_FTR_L3CR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) l3cr = _get_L3CR();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if ((prev_l3cr & L3CR_L3E) && l3cr != prev_l3cr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) _set_L3CR(prev_l3cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) cur_freq = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static unsigned int pmac_cpufreq_get_speed(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return cur_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static int pmac_cpufreq_target( struct cpufreq_policy *policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) rc = do_set_cpu_speed(policy, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ppc_proc_freq = cur_freq * 1000ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int pmac_cpufreq_cpu_init(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) cpufreq_generic_init(policy, pmac_cpu_freqs, transition_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static u32 read_gpio(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) const u32 *reg = of_get_property(np, "reg", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (reg == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* That works for all keylargos but shall be fixed properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * some day... The problem is that it seems we can't rely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * on the "reg" property of the GPIO nodes, they are either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * relative to the base of KeyLargo or to the base of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * GPIO space, and the device-tree doesn't help.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) offset = *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (offset < KEYLARGO_GPIO_LEVELS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) offset += KEYLARGO_GPIO_LEVELS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int pmac_cpufreq_suspend(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Ok, this could be made a bit smarter, but let's be robust for now. We
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * always force a speed change to high speed before sleep, to make sure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * we have appropriate voltage and/or bus speed for the wakeup process,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * and to make sure our loops_per_jiffies are "good enough", that is will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * not cause too short delays if we sleep in low speed and wake in high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * speed..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) no_schedule = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) sleep_freq = cur_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (cur_freq == low_freq && !is_pmu_based)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) do_set_cpu_speed(policy, CPUFREQ_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int pmac_cpufreq_resume(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* If we resume, first check if we have a get() function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (get_speed_proc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) cur_freq = get_speed_proc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) cur_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* We don't, hrm... we don't really know our speed here, best
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * is that we force a switch to whatever it was, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * probably high speed due to our suspend() routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) do_set_cpu_speed(policy, sleep_freq == low_freq ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) CPUFREQ_LOW : CPUFREQ_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ppc_proc_freq = cur_freq * 1000ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) no_schedule = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static struct cpufreq_driver pmac_cpufreq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .verify = cpufreq_generic_frequency_table_verify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .target_index = pmac_cpufreq_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .get = pmac_cpufreq_get_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .init = pmac_cpufreq_cpu_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .suspend = pmac_cpufreq_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .resume = pmac_cpufreq_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .flags = CPUFREQ_PM_NO_WARN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .attr = cpufreq_generic_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .name = "powermac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int pmac_cpufreq_init_MacRISC3(struct device_node *cpunode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct device_node *volt_gpio_np = of_find_node_by_name(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) "voltage-gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct device_node *freq_gpio_np = of_find_node_by_name(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) "frequency-gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct device_node *slew_done_gpio_np = of_find_node_by_name(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) "slewing-done");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) const u32 *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * Check to see if it's GPIO driven or PMU only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * The way we extract the GPIO address is slightly hackish, but it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * works well enough for now. We need to abstract the whole GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * stuff sooner or later anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (volt_gpio_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) voltage_gpio = read_gpio(volt_gpio_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (freq_gpio_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) frequency_gpio = read_gpio(freq_gpio_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (slew_done_gpio_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) slew_done_gpio = read_gpio(slew_done_gpio_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* If we use the frequency GPIOs, calculate the min/max speeds based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * on the bus frequencies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (frequency_gpio && slew_done_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int lenp, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) const u32 *freqs, *ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) freqs = of_get_property(cpunode, "bus-frequencies", &lenp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) lenp /= sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (freqs == NULL || lenp != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) pr_err("bus-frequencies incorrect or missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ratio = of_get_property(cpunode, "processor-to-bus-ratio*2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (ratio == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) pr_err("processor-to-bus-ratio*2 missing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Get the min/max bus frequencies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) low_freq = min(freqs[0], freqs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) hi_freq = max(freqs[0], freqs[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Grrrr.. It _seems_ that the device-tree is lying on the low bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * frequency, it claims it to be around 84Mhz on some models while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * it appears to be approx. 101Mhz on all. Let's hack around here...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * fortunately, we don't need to be too precise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (low_freq < 98000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) low_freq = 101000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Convert those to CPU core clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) low_freq = (low_freq * (*ratio)) / 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) hi_freq = (hi_freq * (*ratio)) / 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Now we get the frequencies, we read the GPIO to see what is out current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) rc = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) cur_freq = (rc & 0x01) ? hi_freq : low_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) set_speed_proc = gpios_set_cpu_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* If we use the PMU, look for the min & max frequencies in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * device-tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) value = of_get_property(cpunode, "min-clock-frequency", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (!value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) low_freq = (*value) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* The PowerBook G4 12" (PowerBook6,1) has an error in the device-tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (low_freq < 100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) low_freq *= 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) value = of_get_property(cpunode, "max-clock-frequency", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) hi_freq = (*value) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) set_speed_proc = pmu_set_cpu_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) is_pmu_based = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static int pmac_cpufreq_init_7447A(struct device_node *cpunode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct device_node *volt_gpio_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (of_get_property(cpunode, "dynamic-power-step", NULL) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (volt_gpio_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) voltage_gpio = read_gpio(volt_gpio_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) of_node_put(volt_gpio_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (!voltage_gpio){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pr_err("missing cpu-vcore-select gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* OF only reports the high frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) hi_freq = cur_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) low_freq = cur_freq/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Read actual frequency from CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) cur_freq = dfs_get_cpu_speed();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) set_speed_proc = dfs_set_cpu_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) get_speed_proc = dfs_get_cpu_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int pmac_cpufreq_init_750FX(struct device_node *cpunode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct device_node *volt_gpio_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u32 pvr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) const u32 *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (of_get_property(cpunode, "dynamic-power-step", NULL) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) hi_freq = cur_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) value = of_get_property(cpunode, "reduced-clock-frequency", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (!value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) low_freq = (*value) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (volt_gpio_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) voltage_gpio = read_gpio(volt_gpio_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) of_node_put(volt_gpio_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) pvr = mfspr(SPRN_PVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) has_cpu_l2lve = !((pvr & 0xf00) == 0x100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) set_speed_proc = cpu_750fx_cpu_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) get_speed_proc = cpu_750fx_get_cpu_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) cur_freq = cpu_750fx_get_cpu_speed();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Currently, we support the following machines:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * - Titanium PowerBook 500 (PMU based, 300Mhz & 500Mhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * - iBook2 500/600 (PMU based, 400Mhz & 500/600Mhz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * - iBook2 700 (CPU based, 400Mhz & 700Mhz, support low voltage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * - Recent MacRISC3 laptops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * - All new machines with 7447A CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int __init pmac_cpufreq_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct device_node *cpunode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) const u32 *value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (strstr(boot_command_line, "nocpufreq"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* Get first CPU node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) cpunode = of_cpu_device_node_get(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (!cpunode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Get current cpu clock freq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) value = of_get_property(cpunode, "clock-frequency", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) cur_freq = (*value) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* Check for 7447A based MacRISC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (of_machine_is_compatible("MacRISC3") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) of_get_property(cpunode, "dynamic-power-step", NULL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PVR_VER(mfspr(SPRN_PVR)) == 0x8003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pmac_cpufreq_init_7447A(cpunode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* Allow dynamic switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) transition_latency = 8000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) pmac_cpufreq_driver.flags &= ~CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* Check for other MacRISC3 machines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) } else if (of_machine_is_compatible("PowerBook3,4") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) of_machine_is_compatible("PowerBook3,5") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) of_machine_is_compatible("MacRISC3")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) pmac_cpufreq_init_MacRISC3(cpunode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Else check for iBook2 500/600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) } else if (of_machine_is_compatible("PowerBook4,1")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) hi_freq = cur_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) low_freq = 400000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) set_speed_proc = pmu_set_cpu_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) is_pmu_based = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Else check for TiPb 550 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) else if (of_machine_is_compatible("PowerBook3,3") && cur_freq == 550000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) hi_freq = cur_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) low_freq = 500000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) set_speed_proc = pmu_set_cpu_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) is_pmu_based = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Else check for TiPb 400 & 500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) else if (of_machine_is_compatible("PowerBook3,2")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* We only know about the 400 MHz and the 500Mhz model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * they both have 300 MHz as low frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (cur_freq < 350000 || cur_freq > 550000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) hi_freq = cur_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) low_freq = 300000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) set_speed_proc = pmu_set_cpu_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) is_pmu_based = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* Else check for 750FX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) else if (PVR_VER(mfspr(SPRN_PVR)) == 0x7000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) pmac_cpufreq_init_750FX(cpunode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) of_node_put(cpunode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (set_speed_proc == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) pmac_cpu_freqs[CPUFREQ_LOW].frequency = low_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) pmac_cpu_freqs[CPUFREQ_HIGH].frequency = hi_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ppc_proc_freq = cur_freq * 1000ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) pr_info("Registering PowerMac CPU frequency driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) pr_info("Low: %d Mhz, High: %d Mhz, Boot: %d Mhz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) low_freq/1000, hi_freq/1000, cur_freq/1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return cpufreq_register_driver(&pmac_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) module_init(pmac_cpufreq_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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