^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * CPUFreq support for Armada 370/XP platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012-2016 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Yehuda Yitschak <yehuday@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Gregory Clement <gregory.clement@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define pr_fmt(fmt) "mvebu-pmsu: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pm_opp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/resource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static int __init armada_xp_pmsu_cpufreq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int ret, cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (!of_machine_is_compatible("marvell,armadaxp"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * In order to have proper cpufreq handling, we need to ensure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * that the Device Tree description of the CPU clock includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * the definition of the PMU DFS registers. If not, we do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * register the clock notifier and the cpufreq driver. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * piece of code is only for compatibility with old Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Trees.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) np = of_find_compatible_node(NULL, NULL, "marvell,armada-xp-cpu-clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ret = of_address_to_resource(np, 1, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) pr_warn(FW_WARN "not enabling cpufreq, deprecated armada-xp-cpu-clock binding\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * For each CPU, this loop registers the operating points
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * supported (which are the nominal CPU frequency and half of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * it), and registers the clock notifier that will take care
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * of doing the PMSU part of a frequency transition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct device *cpu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) cpu_dev = get_cpu_device(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (!cpu_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pr_err("Cannot get CPU %d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clk = clk_get(cpu_dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pr_err("Cannot get clock for CPU %d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk) / 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dev_pm_opp_remove(cpu_dev, clk_get_rate(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dev_err(cpu_dev, "Failed to register OPPs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ret = dev_pm_opp_set_sharing_cpus(cpu_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) cpumask_of(cpu_dev->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_err(cpu_dev, "%s: failed to mark OPPs as shared: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) device_initcall(armada_xp_pmsu_cpufreq_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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