^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_opp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MIN_VOLT_SHIFT (100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MAX_VOLT_SHIFT (200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MAX_VOLT_LIMIT (1150000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VOLT_TOL (10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * The struct mtk_cpu_dvfs_info holds necessary information for doing CPU DVFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * on each CPU power/clock domain of Mediatek SoCs. Each CPU cluster in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Mediatek SoCs has two voltage inputs, Vproc and Vsram. In some cases the two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * voltage inputs need to be controlled under a hardware limitation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 100mV < Vsram - Vproc < 200mV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * When scaling the clock frequency of a CPU clock domain, the clock source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * needs to be switched to another stable PLL clock temporarily until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * the original PLL becomes stable at target frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct mtk_cpu_dvfs_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct cpumask cpus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct device *cpu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct regulator *proc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct regulator *sram_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct clk *cpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct clk *inter_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct list_head list_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int intermediate_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) bool need_voltage_tracking;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static LIST_HEAD(dvfs_info_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static struct mtk_cpu_dvfs_info *mtk_cpu_dvfs_info_lookup(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct mtk_cpu_dvfs_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) list_for_each_entry(info, &dvfs_info_list, list_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (cpumask_test_cpu(cpu, &info->cpus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int mtk_cpufreq_voltage_tracking(struct mtk_cpu_dvfs_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int new_vproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct regulator *proc_reg = info->proc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct regulator *sram_reg = info->sram_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int old_vproc, old_vsram, new_vsram, vsram, vproc, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) old_vproc = regulator_get_voltage(proc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (old_vproc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return old_vproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Vsram should not exceed the maximum allowed voltage of SoC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) new_vsram = min(new_vproc + MIN_VOLT_SHIFT, MAX_VOLT_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (old_vproc < new_vproc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * When scaling up voltages, Vsram and Vproc scale up step
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * by step. At each step, set Vsram to (Vproc + 200mV) first,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * then set Vproc to (Vsram - 100mV).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Keep doing it until Vsram and Vproc hit target voltages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) old_vsram = regulator_get_voltage(sram_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (old_vsram < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pr_err("%s: invalid Vsram value: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __func__, old_vsram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return old_vsram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) old_vproc = regulator_get_voltage(proc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (old_vproc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pr_err("%s: invalid Vproc value: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __func__, old_vproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return old_vproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) vsram = min(new_vsram, old_vproc + MAX_VOLT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) vsram = MAX_VOLT_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * If the target Vsram hits the maximum voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * try to set the exact voltage value first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = regulator_set_voltage(sram_reg, vsram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) vsram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ret = regulator_set_voltage(sram_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) vsram - VOLT_TOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) vsram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) vproc = new_vproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = regulator_set_voltage(sram_reg, vsram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) vsram + VOLT_TOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) vproc = vsram - MIN_VOLT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret = regulator_set_voltage(proc_reg, vproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) vproc + VOLT_TOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) regulator_set_voltage(sram_reg, old_vsram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) old_vsram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) } while (vproc < new_vproc || vsram < new_vsram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) } else if (old_vproc > new_vproc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * When scaling down voltages, Vsram and Vproc scale down step
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * by step. At each step, set Vproc to (Vsram - 200mV) first,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * then set Vproc to (Vproc + 100mV).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Keep doing it until Vsram and Vproc hit target voltages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) old_vproc = regulator_get_voltage(proc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (old_vproc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pr_err("%s: invalid Vproc value: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) __func__, old_vproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return old_vproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) old_vsram = regulator_get_voltage(sram_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (old_vsram < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) pr_err("%s: invalid Vsram value: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) __func__, old_vsram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return old_vsram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) vproc = max(new_vproc, old_vsram - MAX_VOLT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = regulator_set_voltage(proc_reg, vproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) vproc + VOLT_TOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (vproc == new_vproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) vsram = new_vsram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) vsram = max(new_vsram, vproc + MIN_VOLT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (vsram + VOLT_TOL >= MAX_VOLT_LIMIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) vsram = MAX_VOLT_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * If the target Vsram hits the maximum voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * try to set the exact voltage value first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = regulator_set_voltage(sram_reg, vsram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) vsram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = regulator_set_voltage(sram_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) vsram - VOLT_TOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) vsram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = regulator_set_voltage(sram_reg, vsram,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) vsram + VOLT_TOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) regulator_set_voltage(proc_reg, old_vproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) old_vproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) } while (vproc > new_vproc + VOLT_TOL ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) vsram > new_vsram + VOLT_TOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int mtk_cpufreq_set_voltage(struct mtk_cpu_dvfs_info *info, int vproc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (info->need_voltage_tracking)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return mtk_cpufreq_voltage_tracking(info, vproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return regulator_set_voltage(info->proc_reg, vproc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) vproc + VOLT_TOL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int mtk_cpufreq_set_target(struct cpufreq_policy *policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct cpufreq_frequency_table *freq_table = policy->freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct clk *cpu_clk = policy->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct clk *armpll = clk_get_parent(cpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct mtk_cpu_dvfs_info *info = policy->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct device *cpu_dev = info->cpu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct dev_pm_opp *opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) long freq_hz, old_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int vproc, old_vproc, inter_vproc, target_vproc, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) inter_vproc = info->intermediate_voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) old_freq_hz = clk_get_rate(cpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) old_vproc = regulator_get_voltage(info->proc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (old_vproc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pr_err("%s: invalid Vproc value: %d\n", __func__, old_vproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return old_vproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) freq_hz = freq_table[index].frequency * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (IS_ERR(opp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pr_err("cpu%d: failed to find OPP for %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) policy->cpu, freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return PTR_ERR(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) vproc = dev_pm_opp_get_voltage(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_pm_opp_put(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * If the new voltage or the intermediate voltage is higher than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * current voltage, scale up voltage first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) target_vproc = (inter_vproc > vproc) ? inter_vproc : vproc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (old_vproc < target_vproc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = mtk_cpufreq_set_voltage(info, target_vproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pr_err("cpu%d: failed to scale up voltage!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) policy->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) mtk_cpufreq_set_voltage(info, old_vproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Reparent the CPU clock to intermediate clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ret = clk_set_parent(cpu_clk, info->inter_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) pr_err("cpu%d: failed to re-parent cpu clock!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) policy->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) mtk_cpufreq_set_voltage(info, old_vproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Set the original PLL to target rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = clk_set_rate(armpll, freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pr_err("cpu%d: failed to scale cpu clock rate!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) policy->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) clk_set_parent(cpu_clk, armpll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mtk_cpufreq_set_voltage(info, old_vproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Set parent of CPU clock back to the original PLL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = clk_set_parent(cpu_clk, armpll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pr_err("cpu%d: failed to re-parent cpu clock!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) policy->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mtk_cpufreq_set_voltage(info, inter_vproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * If the new voltage is lower than the intermediate voltage or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * original voltage, scale down to the new voltage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (vproc < inter_vproc || vproc < old_vproc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = mtk_cpufreq_set_voltage(info, vproc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pr_err("cpu%d: failed to scale down voltage!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) policy->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) clk_set_parent(cpu_clk, info->inter_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) clk_set_rate(armpll, old_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) clk_set_parent(cpu_clk, armpll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define DYNAMIC_POWER "dynamic-power-coefficient"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int mtk_cpu_dvfs_info_init(struct mtk_cpu_dvfs_info *info, int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct device *cpu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct regulator *proc_reg = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct regulator *sram_reg = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct clk *cpu_clk = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct clk *inter_clk = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct dev_pm_opp *opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) cpu_dev = get_cpu_device(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (!cpu_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pr_err("failed to get cpu%d device\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) cpu_clk = clk_get(cpu_dev, "cpu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (IS_ERR(cpu_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (PTR_ERR(cpu_clk) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pr_warn("cpu clk for cpu%d not ready, retry.\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) pr_err("failed to get cpu clk for cpu%d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ret = PTR_ERR(cpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) inter_clk = clk_get(cpu_dev, "intermediate");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (IS_ERR(inter_clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (PTR_ERR(inter_clk) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pr_warn("intermediate clk for cpu%d not ready, retry.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) pr_err("failed to get intermediate clk for cpu%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = PTR_ERR(inter_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) proc_reg = regulator_get_optional(cpu_dev, "proc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (IS_ERR(proc_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (PTR_ERR(proc_reg) == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pr_warn("proc regulator for cpu%d not ready, retry.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pr_err("failed to get proc regulator for cpu%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ret = PTR_ERR(proc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Both presence and absence of sram regulator are valid cases. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) sram_reg = regulator_get_exclusive(cpu_dev, "sram");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Get OPP-sharing information from "operating-points-v2" bindings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, &info->cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pr_err("failed to get OPP-sharing information for cpu%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret = dev_pm_opp_of_cpumask_add_table(&info->cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) pr_warn("no OPP table for cpu%d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) goto out_free_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Search a safe voltage for intermediate frequency. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) rate = clk_get_rate(inter_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (IS_ERR(opp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pr_err("failed to get intermediate opp for cpu%d\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = PTR_ERR(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) goto out_free_opp_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) info->intermediate_voltage = dev_pm_opp_get_voltage(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_pm_opp_put(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) info->cpu_dev = cpu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) info->proc_reg = proc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) info->sram_reg = IS_ERR(sram_reg) ? NULL : sram_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) info->cpu_clk = cpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) info->inter_clk = inter_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * If SRAM regulator is present, software "voltage tracking" is needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * for this CPU power domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) info->need_voltage_tracking = !IS_ERR(sram_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) out_free_opp_table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_pm_opp_of_cpumask_remove_table(&info->cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) out_free_resources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!IS_ERR(proc_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) regulator_put(proc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (!IS_ERR(sram_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) regulator_put(sram_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (!IS_ERR(cpu_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) clk_put(cpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (!IS_ERR(inter_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) clk_put(inter_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static void mtk_cpu_dvfs_info_release(struct mtk_cpu_dvfs_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (!IS_ERR(info->proc_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) regulator_put(info->proc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!IS_ERR(info->sram_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) regulator_put(info->sram_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!IS_ERR(info->cpu_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) clk_put(info->cpu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!IS_ERR(info->inter_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) clk_put(info->inter_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev_pm_opp_of_cpumask_remove_table(&info->cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int mtk_cpufreq_init(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct mtk_cpu_dvfs_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct cpufreq_frequency_table *freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) info = mtk_cpu_dvfs_info_lookup(policy->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pr_err("dvfs info for cpu%d is not initialized.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) policy->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pr_err("failed to init cpufreq table for cpu%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) policy->cpu, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) cpumask_copy(policy->cpus, &info->cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) policy->freq_table = freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) policy->driver_data = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) policy->clk = info->cpu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_pm_opp_of_register_em(info->cpu_dev, policy->cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int mtk_cpufreq_exit(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct mtk_cpu_dvfs_info *info = policy->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev_pm_opp_free_cpufreq_table(info->cpu_dev, &policy->freq_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static struct cpufreq_driver mtk_cpufreq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) CPUFREQ_IS_COOLING_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .verify = cpufreq_generic_frequency_table_verify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .target_index = mtk_cpufreq_set_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .get = cpufreq_generic_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .init = mtk_cpufreq_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .exit = mtk_cpufreq_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .name = "mtk-cpufreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .attr = cpufreq_generic_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static int mtk_cpufreq_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct mtk_cpu_dvfs_info *info, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) int cpu, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) info = mtk_cpu_dvfs_info_lookup(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) goto release_dvfs_info_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ret = mtk_cpu_dvfs_info_init(info, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) "failed to initialize dvfs info for cpu%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) goto release_dvfs_info_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) list_add(&info->list_head, &dvfs_info_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ret = cpufreq_register_driver(&mtk_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_err(&pdev->dev, "failed to register mtk cpufreq driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) goto release_dvfs_info_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) release_dvfs_info_list:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) list_for_each_entry_safe(info, tmp, &dvfs_info_list, list_head) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) mtk_cpu_dvfs_info_release(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) list_del(&info->list_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static struct platform_driver mtk_cpufreq_platdrv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .name = "mtk-cpufreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .probe = mtk_cpufreq_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* List of machines supported by this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static const struct of_device_id mtk_cpufreq_machines[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) { .compatible = "mediatek,mt2701", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) { .compatible = "mediatek,mt2712", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) { .compatible = "mediatek,mt7622", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) { .compatible = "mediatek,mt7623", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) { .compatible = "mediatek,mt817x", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { .compatible = "mediatek,mt8173", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { .compatible = "mediatek,mt8176", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { .compatible = "mediatek,mt8183", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { .compatible = "mediatek,mt8516", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MODULE_DEVICE_TABLE(of, mtk_cpufreq_machines);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int __init mtk_cpufreq_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) np = of_find_node_by_path("/");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) match = of_match_node(mtk_cpufreq_machines, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pr_debug("Machine is not compatible with mtk-cpufreq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) err = platform_driver_register(&mtk_cpufreq_platdrv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * Since there's no place to hold device registration code and no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * device tree based way to match cpufreq driver yet, both the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * and the device registration codes are put here to handle defer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * probing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) pdev = platform_device_register_simple("mtk-cpufreq", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (IS_ERR(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) pr_err("failed to register mtk-cpufreq platform device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return PTR_ERR(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) device_initcall(mtk_cpufreq_driver_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) MODULE_DESCRIPTION("MediaTek CPUFreq driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) MODULE_AUTHOR("Pi-Cheng Chen <pi-cheng.chen@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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