^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011 Dmitry Eremin-Solenikov
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * that is iMac G5 and latest single CPU desktop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DBG(fmt...) pr_debug(fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* see 970FX user manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SCOM_PCR 0x0aa001 /* PCR scom addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCR_SPEED_MASK 0x000e0000U /* speed mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCR_SPEED_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCR_TARGET_TIME_MASK 0x00006000U /* target time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SCOM_PSR 0x408001 /* PSR scom addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* warning: PSR is a 64 bits register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PSR_CUR_SPEED_SHIFT (56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * The G5 only supports two frequencies (Quarter speed is not supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CPUFREQ_HIGH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CPUFREQ_LOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static struct cpufreq_frequency_table maple_cpu_freqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {0, CPUFREQ_HIGH, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {0, CPUFREQ_LOW, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {0, 0, CPUFREQ_TABLE_END},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Power mode data is an array of the 32 bits PCR values to use for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * the various frequencies, retrieved from the device-tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int maple_pmode_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const u32 *maple_pmode_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int maple_pmode_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * SCOM based frequency switching for 970FX rev3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int maple_scom_switch_freq(int speed_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Clear PCR high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) scom970_write(SCOM_PCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Clear PCR low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Set PCR low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) scom970_write(SCOM_PCR, PCR_HILO_SELECT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) maple_pmode_data[speed_mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Wait for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) for (to = 0; to < 10; to++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned long psr = scom970_read(SCOM_PSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if ((psr & PSR_CMD_RECEIVED) == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) (((psr >> PSR_CUR_SPEED_SHIFT) ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (maple_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (psr & PSR_CMD_COMPLETED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) maple_pmode_cur = speed_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ppc_proc_freq = maple_cpu_freqs[speed_mode].frequency * 1000ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int maple_scom_query_freq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long psr = scom970_read(SCOM_PSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) for (i = 0; i <= maple_pmode_max; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) (maple_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Common interface to the cpufreq core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int maple_cpufreq_target(struct cpufreq_policy *policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return maple_scom_switch_freq(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static unsigned int maple_cpufreq_get_speed(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return maple_cpu_freqs[maple_pmode_cur].frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int maple_cpufreq_cpu_init(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) cpufreq_generic_init(policy, maple_cpu_freqs, 12000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct cpufreq_driver maple_cpufreq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .name = "maple",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .flags = CPUFREQ_CONST_LOOPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .init = maple_cpufreq_cpu_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .verify = cpufreq_generic_frequency_table_verify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .target_index = maple_cpufreq_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .get = maple_cpufreq_get_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .attr = cpufreq_generic_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int __init maple_cpufreq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct device_node *cpunode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int psize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned long max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) const u32 *valp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 pvr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * Behave here like powermac driver which checks machine compatibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * to ease merging of two drivers in future.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (!of_machine_is_compatible("Momentum,Maple") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) !of_machine_is_compatible("Momentum,Apache"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Get first CPU node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) cpunode = of_cpu_device_node_get(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (cpunode == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pr_err("Can't find any CPU 0 node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) goto bail_noprops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Check 970FX for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* we actually don't care on which CPU to access PVR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pvr_hi = PVR_VER(mfspr(SPRN_PVR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (pvr_hi != 0x3c && pvr_hi != 0x44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pr_err("Unsupported CPU version (%x)\n", pvr_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) goto bail_noprops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Look for the powertune data in the device-tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * On Maple this property is provided by PIBS in dual-processor config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * not provided by PIBS in CPU0 config and also not provided by SLOF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * so YMMV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) maple_pmode_data = of_get_property(cpunode, "power-mode-data", &psize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!maple_pmode_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) DBG("No power-mode-data !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) goto bail_noprops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) maple_pmode_max = psize / sizeof(u32) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * From what I see, clock-frequency is always the maximal frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * The current driver can not slew sysclk yet, so we really only deal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * with powertune steps for now. We also only implement full freq and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * half freq in this version. So far, I haven't yet seen a machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * supporting anything else.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) valp = of_get_property(cpunode, "clock-frequency", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!valp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) goto bail_noprops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) max_freq = (*valp)/1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) maple_cpu_freqs[0].frequency = max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) maple_cpu_freqs[1].frequency = max_freq/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Force apply current frequency to make sure everything is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * sync (voltage is right for example). Firmware may leave us with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * a strange setting ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) maple_pmode_cur = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) maple_scom_switch_freq(maple_scom_query_freq());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pr_info("Registering Maple CPU frequency driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pr_info("Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) maple_cpu_freqs[1].frequency/1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) maple_cpu_freqs[0].frequency/1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) maple_cpu_freqs[maple_pmode_cur].frequency/1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) rc = cpufreq_register_driver(&maple_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) bail_noprops:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) of_node_put(cpunode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) module_init(maple_cpufreq_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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