^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_opp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PU_SOC_VOLTAGE_NORMAL 1250000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PU_SOC_VOLTAGE_HIGH 1275000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FREQ_1P2_GHZ 1200000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static struct regulator *arm_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static struct regulator *pu_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static struct regulator *soc_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum IMX6_CPUFREQ_CLKS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) ARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PLL1_SYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PLL1_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PLL2_PFD2_396M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* MX6UL requires two more clks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PLL2_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) SECONDARY_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX6Q_CPUFREQ_CLK_NUM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX6UL_CPUFREQ_CLK_NUM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static struct clk_bulk_data clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { .id = "arm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { .id = "pll1_sys" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { .id = "step" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { .id = "pll1_sw" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { .id = "pll2_pfd2_396m" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { .id = "pll2_bus" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { .id = "secondary_sel" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct device *cpu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct cpufreq_frequency_table *freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static unsigned int max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static unsigned int transition_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static u32 *imx6_soc_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static u32 soc_opp_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct dev_pm_opp *opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long freq_hz, volt, volt_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int old_freq, new_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) bool pll1_sys_temp_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) new_freq = freq_table[index].frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) freq_hz = new_freq * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) old_freq = clk_get_rate(clks[ARM].clk) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (IS_ERR(opp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return PTR_ERR(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) volt = dev_pm_opp_get_voltage(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) dev_pm_opp_put(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) volt_old = regulator_get_voltage(arm_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) old_freq / 1000, volt_old / 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) new_freq / 1000, volt / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* scaling up? scale voltage before frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (new_freq > old_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (!IS_ERR(pu_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ret = regulator_set_voltage_tol(arm_reg, volt, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dev_err(cpu_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "failed to scale vddarm up: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * The setpoints are selected per PLL/PDF frequencies, so we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * reprogram PLL for frequency scaling. The procedure of reprogramming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * PLL1 is as below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * flow is slightly different from other i.MX6 OSC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * - Disable pll2_pfd2_396m_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (of_machine_is_compatible("fsl,imx6ul") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) of_machine_is_compatible("fsl,imx6ull")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * When changing pll1_sw_clk's parent to pll1_sys_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * CPU may run at higher than 528MHz, this will lead to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * the system unstable if the voltage is lower than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * voltage of 528MHz, so lower the CPU frequency to one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * half before changing CPU frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) clk_set_parent(clks[SECONDARY_SEL].clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) clks[PLL2_BUS].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) clk_set_parent(clks[SECONDARY_SEL].clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) clks[PLL2_PFD2_396M].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* pll1_sys needs to be enabled for divider rate change to work. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pll1_sys_temp_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) clk_prepare_enable(clks[PLL1_SYS].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Ensure the arm clock divider is what we expect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int ret1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_warn(cpu_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "failed to restore vddarm voltage: %d\n", ret1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* PLL1 is only needed until after ARM-PODF is set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (pll1_sys_temp_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) clk_disable_unprepare(clks[PLL1_SYS].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* scaling down? scale voltage after frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (new_freq < old_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = regulator_set_voltage_tol(arm_reg, volt, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_warn(cpu_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "failed to scale vddarm down: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!IS_ERR(pu_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) policy->clk = clks[ARM].clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) cpufreq_generic_init(policy, freq_table, transition_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) policy->suspend_freq = max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dev_pm_opp_of_register_em(cpu_dev, policy->cpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct cpufreq_driver imx6q_cpufreq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) CPUFREQ_IS_COOLING_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .verify = cpufreq_generic_frequency_table_verify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .target_index = imx6q_set_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .get = cpufreq_generic_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .init = imx6q_cpufreq_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .name = "imx6q-cpufreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .attr = cpufreq_generic_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .suspend = cpufreq_generic_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define OCOTP_CFG3 0x440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define OCOTP_CFG3_SPEED_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define OCOTP_CFG3_SPEED_1P2GHZ 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define OCOTP_CFG3_SPEED_996MHZ 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define OCOTP_CFG3_SPEED_852MHZ 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int imx6q_opp_check_speed_grading(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_err(dev, "failed to map ocotp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * SPEED_GRADING[1:0] defines the max speed of ARM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * 2b'11: 1200000000Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * 2b'10: 996000000Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * 2b'00: 792000000Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * We need to set the max speed of ARM according to fuse map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) val = readl_relaxed(base + OCOTP_CFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) val >>= OCOTP_CFG3_SPEED_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) val &= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (val < OCOTP_CFG3_SPEED_996MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (dev_pm_opp_disable(dev, 996000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dev_warn(dev, "failed to disable 996MHz OPP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (of_machine_is_compatible("fsl,imx6q") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) of_machine_is_compatible("fsl,imx6qp")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (val != OCOTP_CFG3_SPEED_852MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (dev_pm_opp_disable(dev, 852000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dev_warn(dev, "failed to disable 852MHz OPP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (val != OCOTP_CFG3_SPEED_1P2GHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (dev_pm_opp_disable(dev, 1200000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_warn(dev, "failed to disable 1.2GHz OPP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int imx6ul_opp_check_speed_grading(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) np = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "fsl,imx6ull-ocotp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev_err(dev, "failed to map ocotp\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) val = readl_relaxed(base + OCOTP_CFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Speed GRADING[1:0] defines the max speed of ARM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * 2b'00: Reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * 2b'01: 528000000Hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * 2b'11: 900000000Hz on i.MX6ULL only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * We need to set the max speed of ARM according to fuse map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) val >>= OCOTP_CFG3_SPEED_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) val &= 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (of_machine_is_compatible("fsl,imx6ul")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (dev_pm_opp_disable(dev, 696000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_warn(dev, "failed to disable 696MHz OPP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (of_machine_is_compatible("fsl,imx6ull")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (dev_pm_opp_disable(dev, 792000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_warn(dev, "failed to disable 792MHz OPP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (dev_pm_opp_disable(dev, 900000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_warn(dev, "failed to disable 900MHz OPP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int imx6q_cpufreq_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct dev_pm_opp *opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned long min_volt, max_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int num, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) const struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) const __be32 *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 nr, i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) cpu_dev = get_cpu_device(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (!cpu_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pr_err("failed to get cpu0 device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) np = of_node_get(cpu_dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_err(cpu_dev, "failed to find cpu0 node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (of_machine_is_compatible("fsl,imx6ul") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) of_machine_is_compatible("fsl,imx6ull"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) num_clks = IMX6UL_CPUFREQ_CLK_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) num_clks = IMX6Q_CPUFREQ_CLK_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = clk_bulk_get(cpu_dev, num_clks, clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) goto put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) arm_reg = regulator_get(cpu_dev, "arm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pu_reg = regulator_get_optional(cpu_dev, "pu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) soc_reg = regulator_get(cpu_dev, "soc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PTR_ERR(soc_reg) == -EPROBE_DEFER ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PTR_ERR(pu_reg) == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret = -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev_dbg(cpu_dev, "regulators not ready, defer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) goto put_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_err(cpu_dev, "failed to get regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) goto put_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = dev_pm_opp_of_add_table(cpu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) goto put_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (of_machine_is_compatible("fsl,imx6ul") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) of_machine_is_compatible("fsl,imx6ull")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = imx6ul_opp_check_speed_grading(cpu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = imx6q_opp_check_speed_grading(cpu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (ret != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dev_err(cpu_dev, "failed to read ocotp: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) goto out_free_opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) num = dev_pm_opp_get_opp_count(cpu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (num < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) goto out_free_opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) goto out_free_opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Make imx6_soc_volt array's size same as arm opp number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (imx6_soc_volt == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) goto free_freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) prop = of_find_property(np, "fsl,soc-operating-points", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (!prop || !prop->value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) goto soc_opp_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * Each OPP is a set of tuples consisting of frequency and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * voltage like <freq-kHz vol-uV>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) nr = prop->length / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (nr % 2 || (nr / 2) < num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) goto soc_opp_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) for (j = 0; j < num; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) val = prop->value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) for (i = 0; i < nr / 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) unsigned long freq = be32_to_cpup(val++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned long volt = be32_to_cpup(val++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (freq_table[j].frequency == freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) imx6_soc_volt[soc_opp_count++] = volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) soc_opp_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* use fixed soc opp volt if no valid soc opp info found in dtb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (soc_opp_count != num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) for (j = 0; j < num; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (of_property_read_u32(np, "clock-latency", &transition_latency))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) transition_latency = CPUFREQ_ETERNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * Calculate the ramp time for max voltage change in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * VDDSOC and VDDPU regulators.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) transition_latency += ret * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (!IS_ERR(pu_reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) transition_latency += ret * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * OPP is maintained in order of increasing frequency, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * freq_table initialised from OPP is therefore sorted in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * same order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) max_freq = freq_table[--num].frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) opp = dev_pm_opp_find_freq_exact(cpu_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) freq_table[0].frequency * 1000, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) min_volt = dev_pm_opp_get_voltage(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_pm_opp_put(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) max_volt = dev_pm_opp_get_voltage(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) dev_pm_opp_put(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) transition_latency += ret * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev_err(cpu_dev, "failed register driver: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) goto free_freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) free_freq_table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) out_free_opp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dev_pm_opp_of_remove_table(cpu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) put_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!IS_ERR(arm_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) regulator_put(arm_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (!IS_ERR(pu_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) regulator_put(pu_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (!IS_ERR(soc_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) regulator_put(soc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) clk_bulk_put(num_clks, clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) put_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static int imx6q_cpufreq_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) cpufreq_unregister_driver(&imx6q_cpufreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dev_pm_opp_of_remove_table(cpu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) regulator_put(arm_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (!IS_ERR(pu_reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) regulator_put(pu_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) regulator_put(soc_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) clk_bulk_put(num_clks, clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct platform_driver imx6q_cpufreq_platdrv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .name = "imx6q-cpufreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .probe = imx6q_cpufreq_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .remove = imx6q_cpufreq_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) module_platform_driver(imx6q_cpufreq_platdrv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MODULE_ALIAS("platform:imx6q-cpufreq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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