^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2019 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/nvmem-consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_opp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "cpufreq-dt.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OCOTP_CFG3_SPEED_GRADE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OCOTP_CFG3_SPEED_GRADE_MASK (0x3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK (0xf << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OCOTP_CFG3_MKT_SEGMENT_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX7ULP_MAX_RUN_FREQ 528000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* cpufreq-dt device registered by imx-cpufreq-dt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static struct platform_device *cpufreq_dt_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static struct opp_table *cpufreq_opp_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct device *cpu_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum IMX7ULP_CPUFREQ_CLKS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) SCS_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) HSRUN_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) HSRUN_SCS_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) FIRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static struct clk_bulk_data imx7ulp_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { .id = "arm" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { .id = "core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { .id = "scs_sel" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { .id = "hsrun_core" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) { .id = "hsrun_scs_sel" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { .id = "firc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static unsigned int imx7ulp_get_intermediate(struct cpufreq_policy *policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return clk_get_rate(imx7ulp_clks[FIRC].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int imx7ulp_target_intermediate(struct cpufreq_policy *policy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int newfreq = policy->freq_table[index].frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) clk_set_parent(imx7ulp_clks[SCS_SEL].clk, imx7ulp_clks[FIRC].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) clk_set_parent(imx7ulp_clks[HSRUN_SCS_SEL].clk, imx7ulp_clks[FIRC].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (newfreq > IMX7ULP_MAX_RUN_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) clk_set_parent(imx7ulp_clks[ARM].clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) imx7ulp_clks[HSRUN_CORE].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clk_set_parent(imx7ulp_clks[ARM].clk, imx7ulp_clks[CORE].clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct cpufreq_dt_platform_data imx7ulp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .target_intermediate = imx7ulp_target_intermediate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .get_intermediate = imx7ulp_get_intermediate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int imx_cpufreq_dt_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct platform_device *dt_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 cell_value, supported_hw[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) int speed_grade, mkt_segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) cpu_dev = get_cpu_device(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (!of_find_property(cpu_dev->of_node, "cpu-supply", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (of_machine_is_compatible("fsl,imx7ulp")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ret = clk_bulk_get(cpu_dev, ARRAY_SIZE(imx7ulp_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) imx7ulp_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dt_pdev = platform_device_register_data(NULL, "cpufreq-dt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) -1, &imx7ulp_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) sizeof(imx7ulp_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (IS_ERR(dt_pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clk_bulk_put(ARRAY_SIZE(imx7ulp_clks), imx7ulp_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = PTR_ERR(dt_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dev_err(&pdev->dev, "Failed to register cpufreq-dt: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) cpufreq_dt_pdev = dt_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ret = nvmem_cell_read_u32(cpu_dev, "speed_grade", &cell_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (of_machine_is_compatible("fsl,imx8mn") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) of_machine_is_compatible("fsl,imx8mp"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) speed_grade = (cell_value & IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (of_machine_is_compatible("fsl,imx8mp"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) mkt_segment = (cell_value & IMX8MP_OCOTP_CFG3_MKT_SEGMENT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) >> IMX8MP_OCOTP_CFG3_MKT_SEGMENT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Early samples without fuses written report "0 0" which may NOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * match any OPP defined in DT. So clamp to minimum OPP defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * DT to avoid warning for "no OPPs".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Applies to i.MX8M series SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (mkt_segment == 0 && speed_grade == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (of_machine_is_compatible("fsl,imx8mm") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) of_machine_is_compatible("fsl,imx8mq"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) speed_grade = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (of_machine_is_compatible("fsl,imx8mn") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) of_machine_is_compatible("fsl,imx8mp"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) speed_grade = 0xb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) supported_hw[0] = BIT(speed_grade);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) supported_hw[1] = BIT(mkt_segment);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_info(&pdev->dev, "cpu speed grade %d mkt segment %d supported-hw %#x %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) speed_grade, mkt_segment, supported_hw[0], supported_hw[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cpufreq_opp_table = dev_pm_opp_set_supported_hw(cpu_dev, supported_hw, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (IS_ERR(cpufreq_opp_table)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ret = PTR_ERR(cpufreq_opp_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_err(&pdev->dev, "Failed to set supported opp: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) cpufreq_dt_pdev = platform_device_register_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) &pdev->dev, "cpufreq-dt", -1, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (IS_ERR(cpufreq_dt_pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev_pm_opp_put_supported_hw(cpufreq_opp_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = PTR_ERR(cpufreq_dt_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dev_err(&pdev->dev, "Failed to register cpufreq-dt: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int imx_cpufreq_dt_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) platform_device_unregister(cpufreq_dt_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!of_machine_is_compatible("fsl,imx7ulp"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dev_pm_opp_put_supported_hw(cpufreq_opp_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) clk_bulk_put(ARRAY_SIZE(imx7ulp_clks), imx7ulp_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct platform_driver imx_cpufreq_dt_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .probe = imx_cpufreq_dt_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .remove = imx_cpufreq_dt_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .name = "imx-cpufreq-dt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) module_platform_driver(imx_cpufreq_dt_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MODULE_ALIAS("platform:imx-cpufreq-dt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MODULE_DESCRIPTION("Freescale i.MX cpufreq speed grading driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags