^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019 David Lechner <david@lechnology.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Counter driver for Texas Instruments Enhanced Quadrature Encoder Pulse (eQEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/counter.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* 32-bit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define QPOSCNT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define QPOSINIT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define QPOSMAX 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define QPOSCMP 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define QPOSILAT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define QPOSSLAT 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define QPOSLAT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define QUTMR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define QUPRD 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* 16-bit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define QWDTMR 0x0 /* 0x24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define QWDPRD 0x2 /* 0x26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define QDECCTL 0x4 /* 0x28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define QEPCTL 0x6 /* 0x2a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define QCAPCTL 0x8 /* 0x2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define QPOSCTL 0xa /* 0x2e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define QEINT 0xc /* 0x30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define QFLG 0xe /* 0x32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define QCLR 0x10 /* 0x34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define QFRC 0x12 /* 0x36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define QEPSTS 0x14 /* 0x38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define QCTMR 0x16 /* 0x3a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define QCPRD 0x18 /* 0x3c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define QCTMRLAT 0x1a /* 0x3e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define QCPRDLAT 0x1c /* 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define QDECCTL_QSRC_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define QDECCTL_QSRC GENMASK(15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define QDECCTL_SOEN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define QDECCTL_SPSEL BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define QDECCTL_XCR BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define QDECCTL_SWAP BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define QDECCTL_IGATE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define QDECCTL_QAP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define QDECCTL_QBP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define QDECCTL_QIP BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define QDECCTL_QSP BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define QEPCTL_FREE_SOFT GENMASK(15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define QEPCTL_PCRM GENMASK(13, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define QEPCTL_SEI GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define QEPCTL_IEI GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define QEPCTL_SWI BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define QEPCTL_SEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define QEPCTL_IEL GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define QEPCTL_PHEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define QEPCTL_QCLM BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define QEPCTL_UTE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define QEPCTL_WDE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* EQEP Inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) TI_EQEP_SIGNAL_QEPA, /* QEPA/XCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) TI_EQEP_SIGNAL_QEPB, /* QEPB/XDIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Position Counter Input Modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) TI_EQEP_COUNT_FUNC_QUAD_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) TI_EQEP_COUNT_FUNC_DIR_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) TI_EQEP_COUNT_FUNC_UP_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) TI_EQEP_COUNT_FUNC_DOWN_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) TI_EQEP_SYNAPSE_ACTION_BOTH_EDGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) TI_EQEP_SYNAPSE_ACTION_RISING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) TI_EQEP_SYNAPSE_ACTION_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct ti_eqep_cnt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct counter_device counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct regmap *regmap32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct regmap *regmap16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int ti_eqep_count_read(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct counter_count *count, unsigned long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct ti_eqep_cnt *priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) regmap_read(priv->regmap32, QPOSCNT, &cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *val = cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int ti_eqep_count_write(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct counter_count *count, unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct ti_eqep_cnt *priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) regmap_read(priv->regmap32, QPOSMAX, &max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (val > max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return regmap_write(priv->regmap32, QPOSCNT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int ti_eqep_function_get(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct counter_count *count, size_t *function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct ti_eqep_cnt *priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 qdecctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) regmap_read(priv->regmap16, QDECCTL, &qdecctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *function = (qdecctl & QDECCTL_QSRC) >> QDECCTL_QSRC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int ti_eqep_function_set(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct counter_count *count, size_t function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct ti_eqep_cnt *priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return regmap_write_bits(priv->regmap16, QDECCTL, QDECCTL_QSRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) function << QDECCTL_QSRC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int ti_eqep_action_get(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct counter_synapse *synapse, size_t *action)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct ti_eqep_cnt *priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) size_t function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 qdecctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) err = ti_eqep_function_get(counter, count, &function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) switch (function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case TI_EQEP_COUNT_FUNC_QUAD_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* In quadrature mode, the rising and falling edge of both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * QEPA and QEPB trigger QCLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *action = TI_EQEP_SYNAPSE_ACTION_BOTH_EDGES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case TI_EQEP_COUNT_FUNC_DIR_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* In direction-count mode only rising edge of QEPA is counted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * and QEPB gives direction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) switch (synapse->signal->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case TI_EQEP_SIGNAL_QEPA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *action = TI_EQEP_SYNAPSE_ACTION_RISING_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *action = TI_EQEP_SYNAPSE_ACTION_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) case TI_EQEP_COUNT_FUNC_UP_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case TI_EQEP_COUNT_FUNC_DOWN_COUNT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* In up/down-count modes only QEPA is counted and QEPB is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) switch (synapse->signal->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case TI_EQEP_SIGNAL_QEPA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) err = regmap_read(priv->regmap16, QDECCTL, &qdecctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (qdecctl & QDECCTL_XCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) *action = TI_EQEP_SYNAPSE_ACTION_BOTH_EDGES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) *action = TI_EQEP_SYNAPSE_ACTION_RISING_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *action = TI_EQEP_SYNAPSE_ACTION_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const struct counter_ops ti_eqep_counter_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .count_read = ti_eqep_count_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .count_write = ti_eqep_count_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .function_get = ti_eqep_function_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .function_set = ti_eqep_function_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .action_get = ti_eqep_action_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static ssize_t ti_eqep_position_ceiling_read(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) void *ext_priv, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct ti_eqep_cnt *priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 qposmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) regmap_read(priv->regmap32, QPOSMAX, &qposmax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return sprintf(buf, "%u\n", qposmax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static ssize_t ti_eqep_position_ceiling_write(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) void *ext_priv, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct ti_eqep_cnt *priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) err = kstrtouint(buf, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) regmap_write(priv->regmap32, QPOSMAX, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static ssize_t ti_eqep_position_enable_read(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) void *ext_priv, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct ti_eqep_cnt *priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 qepctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) regmap_read(priv->regmap16, QEPCTL, &qepctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return sprintf(buf, "%u\n", !!(qepctl & QEPCTL_PHEN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static ssize_t ti_eqep_position_enable_write(struct counter_device *counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct counter_count *count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) void *ext_priv, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct ti_eqep_cnt *priv = counter->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) bool res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) err = kstrtobool(buf, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) regmap_write_bits(priv->regmap16, QEPCTL, QEPCTL_PHEN, res ? -1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static struct counter_count_ext ti_eqep_position_ext[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .name = "ceiling",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .read = ti_eqep_position_ceiling_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .write = ti_eqep_position_ceiling_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .name = "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .read = ti_eqep_position_enable_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .write = ti_eqep_position_enable_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static struct counter_signal ti_eqep_signals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [TI_EQEP_SIGNAL_QEPA] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .id = TI_EQEP_SIGNAL_QEPA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .name = "QEPA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) [TI_EQEP_SIGNAL_QEPB] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .id = TI_EQEP_SIGNAL_QEPB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .name = "QEPB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const enum counter_count_function ti_eqep_position_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) [TI_EQEP_COUNT_FUNC_QUAD_COUNT] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) [TI_EQEP_COUNT_FUNC_DIR_COUNT] = COUNTER_COUNT_FUNCTION_PULSE_DIRECTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) [TI_EQEP_COUNT_FUNC_UP_COUNT] = COUNTER_COUNT_FUNCTION_INCREASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) [TI_EQEP_COUNT_FUNC_DOWN_COUNT] = COUNTER_COUNT_FUNCTION_DECREASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const enum counter_synapse_action ti_eqep_position_synapse_actions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) [TI_EQEP_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [TI_EQEP_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) [TI_EQEP_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static struct counter_synapse ti_eqep_position_synapses[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .actions_list = ti_eqep_position_synapse_actions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .num_actions = ARRAY_SIZE(ti_eqep_position_synapse_actions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .signal = &ti_eqep_signals[TI_EQEP_SIGNAL_QEPA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .actions_list = ti_eqep_position_synapse_actions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .num_actions = ARRAY_SIZE(ti_eqep_position_synapse_actions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .signal = &ti_eqep_signals[TI_EQEP_SIGNAL_QEPB],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static struct counter_count ti_eqep_counts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .name = "QPOSCNT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .functions_list = ti_eqep_position_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .num_functions = ARRAY_SIZE(ti_eqep_position_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .synapses = ti_eqep_position_synapses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .num_synapses = ARRAY_SIZE(ti_eqep_position_synapses),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .ext = ti_eqep_position_ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .num_ext = ARRAY_SIZE(ti_eqep_position_ext),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const struct regmap_config ti_eqep_regmap32_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .name = "32-bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .max_register = QUPRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const struct regmap_config ti_eqep_regmap16_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .name = "16-bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .reg_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .val_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .reg_stride = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .max_register = QCPRDLAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int ti_eqep_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct ti_eqep_cnt *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) priv->regmap32 = devm_regmap_init_mmio(dev, base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) &ti_eqep_regmap32_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (IS_ERR(priv->regmap32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return PTR_ERR(priv->regmap32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) priv->regmap16 = devm_regmap_init_mmio(dev, base + 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) &ti_eqep_regmap16_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (IS_ERR(priv->regmap16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return PTR_ERR(priv->regmap16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) priv->counter.name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) priv->counter.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) priv->counter.ops = &ti_eqep_counter_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) priv->counter.counts = ti_eqep_counts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) priv->counter.num_counts = ARRAY_SIZE(ti_eqep_counts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) priv->counter.signals = ti_eqep_signals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) priv->counter.num_signals = ARRAY_SIZE(ti_eqep_signals);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) priv->counter.priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Need to make sure power is turned on. On AM33xx, this comes from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * parent PWMSS bus driver. On AM17xx, this comes from the PSC power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) err = counter_register(&priv->counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int ti_eqep_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct ti_eqep_cnt *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) counter_unregister(&priv->counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static const struct of_device_id ti_eqep_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { .compatible = "ti,am3352-eqep", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MODULE_DEVICE_TABLE(of, ti_eqep_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static struct platform_driver ti_eqep_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .probe = ti_eqep_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .remove = ti_eqep_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .name = "ti-eqep-cnt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .of_match_table = ti_eqep_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) module_platform_driver(ti_eqep_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MODULE_AUTHOR("David Lechner <david@lechnology.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MODULE_DESCRIPTION("TI eQEP counter driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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